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| Number | Title | Issue Date |
| 6178487 | Manipulating disk partitions between disks A method allows manipulation of disk partitions defined by an IBM-compatible partition table. The disk partitions may be located on one or more disks attached to one or more disk drives. Each partition has an associated file system type, such as FAT or HP... | 01/23/2001 |
| 6178480 | Method for operating an array of video storage units A method for increasing the storage capacity of a video server which utilizes an array of disks is disclosed. The server is operated so that the continuity of a plurality of bit streams is maintained. The inventive method has advantageous characteristics ... | 01/23/2001 |
| 6154822 | Method and system for improving data storage and access for programs written in mid-level programming languages A method and system, for improving programs which access a memory array, which accomplish their objects via data-processing equipment programmed to do the following: detect a requested memory operation; determine if the requested operation relates to a pr... | 11/28/2000 |
| 6148363 | Device and method for controlling solid-state memory system A memory system includes an array of solid-state memory devices are in communication with and under the control of a controller module via a device bus with very few lines. This forms an integrated-circuit mass storage system which is contemplated to repl... | 11/14/2000 |
| 6148366 | Storage system which transfers a command and data corresponding to said command subsequent to said command In a storage system comprising a disk controller, a disk unit having queue memory for storing the commands, and network between the disk controller and the disk unit, to decrease a overhead in the write processing in issuing a write command to a disk unit... | 11/14/2000 |
| 6145060 | Data storage device with only internal addressing A data storage device comprises a controller and a semiconductor chip which includes a nonvolatile semiconductor memory having plural storage areas into each of which data is stored, a store instruction signal input terminal to which a store instruction s... | 11/07/2000 |
| 6141728 | Embedded cache manager A method for managing data blocks in a cache buffer defining date block segments, and for automatically transferring data into and out of the cache buffer. A cache list comprises a plurality of entries each including information identifying a correspondin... | 10/31/2000 |
| 6138219 | Method of and operating architectural enhancement for multi-port internally cached dynamic random access memory (AMPIC DRAM) systems, eliminating external control paths and random memory addressing, while providing zero bus contention for DRAM access A technique and system for eliminating bus contention in multi-port internally cached dynamic random access memory (AMPIC DRAM) systems, while eliminating the need for external control paths and random memory addressing, through the use of data header des... | 10/24/2000 |
| 6131150 | Scaled memory allocation system A memory of a computer system is partitioned into a plurality of allocable blocks. Subsets of the allocable blocks are organizing into a plurality of heaps, each heap having a different designated subset of the allocable blocks. The sizes of the allocable... | 10/10/2000 |
| 6131151 | Processing high-speed digital datastreams with reduced memory Methods and apparatus are described for managing high-bandwidth incoming digital data streams, such as MPEG encoded data streams, while reducing memory requirements. Frames of incoming data are divided into smaller slices, for example four slices per fram... | 10/10/2000 |
| 6128700 | System utilizing a DRAM array as a next level cache memory and method for operating same A method and structure for implementing a DRAM memory array as a second level cache memory in a computer system. The computer system includes a central processing unit (CPU), a first level SRAM cache memory, a CPU bus coupled to the CPU, and a second leve... | 10/03/2000 |
| 6119203 | Mechanism for sharing data cache resources between data prefetch operations and normal load/store operations in a data processing system A data processing system (10) provides a mechanism for choosing when the data stream touch (DST) controller (300) is allowed access to the data cache and MMU (50). The mechanism uses a count value to determine at what point in program execution the DST co... | 09/12/2000 |
| 6112276 | Modular disk memory apparatus with high transfer rate A modular disk memory apparatus provides a modularly expandable, multi-gigabyte auxiliary memory for a computer or other host electronic device, and includes multiple, parallel serial data channels to maximize bidirectional data transfer rates between the... | 08/29/2000 |
| 6108758 | Multiple masters in a memory control system A method and apparatus for multiple masters for a memory control system is provided. The memory control system includes a first master, and a memory coupled to the first master using a memory channel. A second master is coupled between the first master an... | 08/22/2000 |
| 6108759 | Manipulation of partitions holding advanced file systems Methods and systems are provided for copying, moving, and resizing disk partitions that contain advanced file systems. Unlike the conventional approach that relies on FDISK and FORMAT, the invention does not destroy user data by wiping the partition clean... | 08/22/2000 |
| 6105116 | Method and apparatus of controlling a disk cache during a degenerated mode of operation A disk cache is controlled to continue duel data writing even during a degenerated mode of operation due to a failure of a cache memory, and also to continue a FAST WRITE process while maintaining reliability for thereby avoiding a drop in performance. If... | 08/15/2000 |
| 6098159 | Information processing apparatus An information processing apparatus is provided which is capable of carrying out the higher memory access. The information processing apparatus includes a memory unit of a synchronous DRAM device which serves to output data synchronously with the supplied... | 08/01/2000 |
| 6098152 | Method and apparatus for miss sequence cache block replacement utilizing a most recently used state A method and apparatus are provided for miss sequence cache block replacement in a cache including a plurality of cache blocks in a computer system. First checking for an invalid block is performed. Responsive to identifying an invalid cache block, the id... | 08/01/2000 |
| 6092153 | Subsettable top level cache As computers execute faster relative to memory, they require more memory bandwidth. Improved memory bandwidth can be achieved by having the compiler group contiguous memory requests. The contiguous words are called packs. The basic working premise of the ... | 07/18/2000 |
| 6088779 | System and method for execution management of computer programs A system for managing execution of a computer program. A domain array is used to reduce the overhead associated with managing multiple instances of a computer program. A portion of virtual address space is reserved for multiple instances of the computer p... | 07/11/2000 |
| 6088778 | Method for manipulating disk partitions A method allows non-destructive manipulation of disk partitions defined by an IBM-compatible partition table. The disk partitions may be located on one or more disks attached to one or more disk drives. Each partition has an associated file system type. A... | 07/11/2000 |
| 6088775 | Data access controller and data access control method A data access controller has an SRAM adapted to hold two ECC blocks so that the SRAM is used efficiently for multiple kinds of processes. At playback of data, writing of ECC block A from a demodulator and an ECC process for ECC block B begin simultaneousl... | 07/11/2000 |
| 6088773 | Checkpoint acquisition accelerating apparatus A novel checkpoint acquisition accelerating apparatus is disclosed. When data are updated on a cache memory, a before-image acquiring section acquires the update address and the previous data and stores them in a before-image storing section. A cache flus... | 07/11/2000 |
| 6078994 | System for maintaining a shared cache in a multi-threaded computer environment In a multi-threaded computing environment, a shared cache system reduces the amount of redundant information stored in memory. A cache memory area provides both global readable data and private writable data to processing threads. A collection mechanism m... | 06/20/2000 |
| 6076144 | Method and apparatus for identifying potential entry points into trace segments An apparatus includes a data array, control logic, an entry candidate table, and a future target table. The control logic is coupled to the data array and adapted to store at least one trace segment of instructions into the data array. The entry candidate... | 06/13/2000 |
| 6076140 | Set associative cache memory system with reduced power consumption A memory design which facilitates incremental and store requests off an applied base address request increases the bandwidth of cache via the use of an internal address generation facility built into the memory's decoding circuitry. The introduction of an... | 06/13/2000 |
| 6073215 | Data processing system having a data prefetch mechanism and method therefor A data processing system (10) includes a mechanism for preventing DST line fetches from occupying the last available entries in a cache miss queue (50) of the data cache and MMU (16). This is done by setting a threshold value of available cache miss queue... | 06/06/2000 |
| 6073213 | Method and apparatus for caching trace segments with multiple entry points An apparatus includes a data array and control logic. The control logic is coupled to the data array and adapted to store at least one trace segment of instructions into the data array. The control logic allows the instructions of the trace segment to be ... | 06/06/2000 |
| 6073216 | System and method for reliable system shutdown after coherency corruption There is disclosed a memory control circuit for use in a processing system containing a plurality of processors coupled to a main memory by a common bus. The memory control circuit is adapted for implementing directory-based coherency in the processing sy... | 06/06/2000 |
| 6070234 | Cacche memory employing dynamically controlled data array start timing and a microcomputer using the same A comparator is constituted such that a hit signal $c;hit is high, before hit check is established in each way of an address array, and such that the hit signal goes low, when a mishit has been established. When a clock frequency is relatively high, th... | 05/30/2000 |
| 6061763 | Memory management system employing multiple buffer caches Computer systems and computer implemented methods are provided for managing memory in a database management system. The computer memory is partitioned into a plurality of buffer caches, each of which is separately addressable. One buffer cache is set asid... | 05/09/2000 |
| 6052765 | Method for optimized placement of virtual volumes on a physical cartridge The present invention provides a method for selectively storing data files on a multiple volume cartridge (MVC) device which maximizes the likelihood of gaps in stored data appearing at the end of a cartridge. All incoming data files are initially stored ... | 04/18/2000 |
| 6021477 | Multiple mode memory module A memory control unit is coupled during use to a system bus for receiving memory addresses therefrom. The memory control unit is further coupled during use to one or more memory units by a second bus that includes a plurality of signal lines for transmitt... | 02/01/2000 |
| 6021461 | Method for reducing power consumption in a set associative cache memory system A method for accessing a cache memory which facilitates incremental and store requests off an applied base address request increases the bandwidth of cache via the use of an internal address generation facility built into the memory's decoding circuitry. ... | 02/01/2000 |
| 6018793 | Single chip controller-memory device including feature-selectable bank I/O and architecture and methods suitable for implementing the same A memory architecture 104 includes a plurality of arrays 200 of memory cells. Addressing circuitry 201 selects a cell of a selected one of arrays 201 for access while feature select circuitry 205 selects an access type to be performed to the selected cell... | 01/25/2000 |
| 6014725 | Method of up-dating the contents of the electronic memory of an electronic appliance To update the memory contents in an electronic memory formed by an EPROM (4) in an electronic apparatus (5) without hardware measures, communication is initiated between the electronic apparatus (5) and a data processing system (1), whereupon code (6) cor... | 01/11/2000 |
| 6014732 | Cache memory with reduced access time A cache with a translation lookaside buffer (TLB) that eliminates the need for retrieval of a physical address tag from the TLB when accessing the cache. The TLB includes two content addressable memories (CAM's). For each new cache line, in the tag portio... | 01/11/2000 |
| 6012127 | Multiprocessor computing apparatus with optional coherency directory A multiprocessor computing apparatus including a plurality of processors each having a cache memory and preferably arranged in nodes on a system bus. A first cache coherency providing mechanism coupled to the processors for achieving system level cache co... | 01/04/2000 |
| 6000011 | Multi-entry fully associative transition cache A method and apparatus for handling commands and data associated therewith includes a data buffer and a command directory. The command directory receives and stores a command from at least one command source, and freely allocates an unused portion of the ... | 12/07/1999 |
| 6000022 | Method and apparatus for coupling signals between two circuits operating in different clock domains A coupling circuit for coupling a first signal generated in a first circuit operating in a first clock domain to a second circuit operating in a second clock domain. The coupling circuit includes a first gate for coupling the first signal to a first logic... | 12/07/1999 |
