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| Number | Title | Issue Date |
| 5088032 | Method and apparatus for routing communications among computer networks An improved method and apparatus for routing data transmissions among computer networks. The computer networks are interconnected with a series of gateway circuits. Each gateway identifies all destination computers to which it is connected and identifies ... | 02/11/1992 |
| 5083268 | System and method for parsing natural language by unifying lexical features of words A method for parsing for natural languages includes a grammar and a lexicon. A knowledge base may be used to define elements in the lexicon. A processor receives single words input by a user and adds them to a sentence under construction. Valid next words... | 01/21/1992 |
| 5079737 | Memory management unit for the MIL-STD 1750 bus A single-chip memory management unit automatically operates in either 1750A or 1750B mode as required, including the provision of memory management and/or block protection, with the added feature of on-chip arbitration between two bus masters that may be ... | 01/07/1992 |
| 5070473 | Microprocessor A wait signal formed by a program wait circuit incorporated in a microprocessor is transmitted to outside circuitry, such as a slave microprocessor or a direct memory access control device. Thereby an outside device assumes the functions of bus master whi... | 12/03/1991 |
| 5063536 | Microprogrammable asynchronous controllers for digital electronic systems An electronic asynchronous digital controller for use in microprocessors, computers and other digital systems. The controller stores a present state code which is classified into one of at least two state code classes, such as in either even or odd parity... | 11/05/1991 |
| 5063534 | Electronic translator capable of producing a sentence by using an entered word as a key word An electronic translating unit has switches for inputting a first language or a second language; a memory consisting of a first memory section for storing words of said first language and addresses of sentences associated with said words, a second memory ... | 11/05/1991 |
| 5062075 | Microcomputer having security memory using test and destruction routines In a single-chip microcomputer having a first memory storing security data and a second memory for storing a test program. The test program includes test routines and a destruction routine to be executed prior to the test routines. The destruction routine... | 10/29/1991 |
| 5057837 | Instruction storage method with a compressed format using a mask word A method and apparatus for storing an instruction word in a compacted form on a storage media, the instruction word having a plurality of instruction fields, features associating with each instruction word, a mask word having a length in bits at least equ... | 10/15/1991 |
| 5053748 | System for the safe and secure transportation of valuable articles, such as bank notes, cheques In a system for transporting bank notes between system terminals in a container for valuables, referred to as a cassette, each cassette is provided with an electronic unit or sealing provision. The electronic unit includes a counter (131) and a memory (13... | 10/01/1991 |
| 5050121 | Communication system which uses characters that represent binary-coded decimal numbers A computer system which creates many styles of character sets whose characters represent either a group of five-bit or a group of eight-bit binary-coded decimal numbers. The character sets are used for common communication, other than handwriting, by peop... | 09/17/1991 |
| 5045993 | Digital signal processor A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction ex... | 09/03/1991 |
| 5045996 | Multiprocessor cache memory housekeeping Each housekeeping command calls for a corresponding combination of write back and flag reset operations. In laundering, a write back operation is performed for owner entries in a specified address set without invalidating those entries. In flushing, a lau... | 09/03/1991 |
| 5043883 | Pipe-lined data processor system of synchronous type having memory devices with buffer memory and input/output data control A pipe-lined data processor system comprising a plurality of processors interconnected in the form of a pipe line, a plurality of memory apparatus connected to each of the processors through output data buses for supplying data to the processors or storin... | 08/27/1991 |
| 5036457 | Bit string compressor with boolean operation processing capability An apparatus and method, for use with a computer, for converting an uncompressed one-dimensional array of binary bits into a compressed binary bit string and/or for processing a Boolean operation on a first and a second compressed bit string. The first an... | 07/30/1991 |
| 5034917 | Computer system including a page mode memory with decreased access time and method of operation thereof A computer system is provided in which memory access time is substantially reduced. After row address strobe (RAS) and column address strobe (CAS) signals are used to select a particular address in a memory during a first memory cycle, the addressed data ... | 07/23/1991 |
| 5034882 | Multiprocessor intelligent cell for a network which provides sensing, bidirectional communications and control A processor is described which is particularly useful in a cell which cell forms part of a network for sensing, communicating and controlling. The processor includes a plurality of sets of registers, each associated with a different processor. Each set of... | 07/23/1991 |
| 5027272 | Method and apparatus for performing double precision vector operations on a coprocessor This invention relates to a system having a coprocessor being utilized by a processor for floating point double precision operations. The coprocessor utilizes one format for storing double precision data, the processor utilizes a second format for storing... | 06/25/1991 |
| 5025366 | Organization of an integrated cache unit for flexible usage in cache system design Methods and apparatus are disclosed for realizing an integrated cache unit which may be flexibly used for cache system design. The preferred embodiment of the invention comprises both a cache memory and a cache controller on a single chip. In accordance w... | 06/18/1991 |
| 5023779 | Distributed processing environment fault isolation The present invention is to designate one of the processors in a multiprocessor control as the master processor. All the other processors report their faults to the master processor. When it receives a fault message, the master processor records the type ... | 06/11/1991 |
| 5023772 | Method and system for storing messages based upon a non-queried name assignment A message storage system and method having a plurality of message storage facilities with storage locations and a storage facility manager. The message storage system assigns individual names to messages as they are input into a message storage facility a... | 06/11/1991 |
| 5021993 | Device for saving and restoring register information Each register of an internal register unit of a microprocessor has a pair of register cells consisting of first and second cells having the same register address. When one of these cells is selected, the other cell non-selected serves as a "back-up cell" ... | 06/04/1991 |
| 5021949 | Method and apparatus for linking an SNA host to a remote SNA host over a packet switched communications network The invention disclosed herein provides the basic operating capabilities of SNA data communications for host based application-to-application sessions across a packet switched network such as the Defense Data Network (DDN). The problem that is presented b... | 06/04/1991 |
| 5021943 | Content independent rule based options negotiations method A methodology for determining the common attributes of two systems or entities is shown. This methodology includes a content independent options negotiation. Tree structures are defined for each entity or system. These tree structures include relational o... | 06/04/1991 |
| 5020003 | Graphics controller image creation The conversion of a drawing instruction into respective pixmap locations resident in main memory is typically performed by a host processor when an associated graphics processor cannot access the main memory. Such conversion is enhanced by employing a com... | 05/28/1991 |
| 5019967 | Pipeline bubble compression in a computer system Bubble compression in a pipelined central processing unit (CPU) of a computer system is provided. A bubble represents a stage in the pipeline that cannot perform any useful work due to the lack of data from an earlier pipeline stage. When a particular pip... | 05/28/1991 |
| 5018098 | Data transfer controlling apparatus for direct memory access A data transfer controlling apparatus for direct memory access comprising one or more first microaddress registers, each of which registers stores microaddress information for program processing of the data transfer for a corresponding channel; a second m... | 05/21/1991 |
| 5010483 | Vector processor capable of indirect addressing A vector processor includes a first read circuit for reading a first vector including a plurality of vectors such as a vector having elements denoting a compare key as a search request and a vector having elements designating a search range associated wit... | 04/23/1991 |
| 5005153 | Data processor integrated on a semiconductor substrate In a semiconductor integrated circuit device having at least two logic blocks each including at least two logic units each having a number of MOS FET's integrated therein, bipolar transistors for driving the MOS FET's are selectively arranged between the ... | 04/02/1991 |
| 5005151 | Interleaved arbitration scheme for interfacing parallel and serial ports to a parallel system port An arbitration circuit (10) is provided for selecting between a serial port (19) and a parallel port (21) for interface with a system port (17) having a system data bus (14) and a system address bus (16). A RAM (12) is supported by the buses (14) and (16)... | 04/02/1991 |
| 5003507 | EPROM emulator for selectively simulating a variety of different paging EPROMs in a test circuit An EPROM emulator makes use of a simple device with a housing connected to a eprom header which serves to connect the device to a circuit board in conjunction with a microprocessor emulator. Inside the housing are paging and data select circuits and a set... | 03/26/1991 |
| 5003470 | Method for tying and untying path access in a CPU-based, layered communications system A method for maintaining the integrity of ties and their associated tie groups in a CPU-based, layered communications subsystem in which the connection endpoints in each layer are denoted by a connection control block (CCB), the relationship between CCBs ... | 03/26/1991 |
| 4999808 | Dual byte order data processor In order that a microprocessor can respond properly to both instruction words and data words that are organized in off-chip memory in accordance with either of two byte order conventions, on-chip circuitry is added which controllably changes the byte orde... | 03/12/1991 |
| 4992933 | SIMD array processor with global instruction control and reprogrammable instruction decoders A single-instruction-multiple-data (SIMD) array processor is described with a multi-dimensional array of processing elements and control logic for issuing global instructions to the array. Each processing element in the array has individually programmable... | 02/12/1991 |
| 4982322 | Apparatus and method for prohibiting access in a multi-cache data processing system to data signal groups being processed by a data processing subsystem To prevent simultaneous usage of selected data signal groups in a data processing system, techniques are described to restrict such usage. First, with each location capable of storing a data signal group, a register cell can be assigned either in the main... | 01/01/1991 |
| 4965882 | Method for operating a parallel processing system and related apparatus A method for operating a parallel processor system implements a beta-partitioning algorithm. According to that method, groups of working memory elements are identified which satisfy each of the conditions of all of several production rules. Then, sequence... | 10/23/1990 |
| 4958275 | Instruction decoder for a variable byte processor An instruction decoder, for a variable byte processor, is capable of making the variable byte processor operate at a high processing speed and high byte efficiency. The instruction decoder includes an instruction register which stores instructions applied... | 09/18/1990 |
| 4958304 | Computer with interface for fast and slow memory circuits A CPU with an interface to two different RAMs which operate at different rates. The interface circuit includes a decoder which examines the addresses from the CPU and determines whether a faster cycle or slower cycle is needed. The slow RAM provides video... | 09/18/1990 |
| 4945475 | Hierarchical file system to provide cataloging and retrieval of data A hierarchical filing system provides a cataloging of data stored in various locations within a memory device. An upside-down tree type structure provides a downwardly expanding cataloging structure wherein directories provide for further branchings. A br... | 07/31/1990 |
| 4945480 | Data domain switching on program address space switching and return The embodiment enables multiple virtual data domains to be accessible to a program executing on a processor. A data domain is a set of virtual address spaces for containing data that can be accessed by an executing program. Two types of data domains are d... | 07/31/1990 |
| 4942551 | Method and apparatus for storing MIDI information in subcode packs The present invention is an apparatus and method for ecoding data in MIDI (Musical Instrument Digital Interface) format on an audio compact disc without affecting the digitized sound stored in the main channel by utilizing what is known as the subcode cha... | 07/17/1990 |
