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| Number | Title | Issue Date |
| 7664936 | Prioritizing thread selection partly based on stall likelihood providing status information of instruction operand register usage at pipeline stages An apparatus for scheduling dispatch of instructions among a plurality of threads being concurrently executed in a multithreading processor is provided. The apparatus includes an instruction decoder that generate register usage information for an instruction from ea... | 02/16/2010 |
| 7464253 | Tracking multiple dependent instructions with instruction queue pointer mapping table linked to a multiple wakeup table by a pointer A method and apparatus for improving the operation of an out-of order computer processor by utilizing and managing instruction wakeup using pointers with an instruction queue payload random-access memory, a mapping table, and a multiple wake-up table. Instructions a... | 12/09/2008 |
| 7454595 | Distributed processor allocation for launching applications in a massively connected processors complex A compute processor allocator architecture for allocating compute processors to run applications in a multiple processor computing apparatus is distributed among a subset of processors within the computing apparatus. Each processor of the subset includes a compute p... | 11/18/2008 |
| 7454593 | Row and column enable signal activation of processing array elements with interconnection logic to simulate bus effect The present invention relates to the control of an array of processing elements in a parallel processor using row and column select lines. For each column in the array, a column select line connects to all of the processing elements in the column. For each row in th... | 11/18/2008 |
| 7451293 | Array of Boolean logic controlled processing elements with concurrent I/O processing and instruction sequencing A computer processor having an integrated instruction sequencer, array of processing engines, and I/O controller. The instruction sequencer sequences instructions from a host, and transfers these instructions to the processing engines, thus directing their operation... | 11/11/2008 |
| 7451298 | Processing exceptions from 64-bit application program executing in 64-bit processor with 32-bit OS kernel by switching to 32-bit processor mode One embodiment of the present invention provides a system that uses an M-bit operating system (OS) kernel to support N-bit user processes. During operation, the system receives an exception. Note that the exception can be any event that needs to be handled by execut... | 11/11/2008 |
| 7441099 | Configurable SIMD processor instruction specifying index to LUT storing information for different operation and memory location for each processing unit Methods and apparatuses for processing a Configurable Single-Instruction-Multiple-Data (CSIMD) instruction are disclosed. In the method, a lookup table (LUT) storing information is provided to support random access of memory locations associated with a plurality of ... | 10/21/2008 |
| 7437540 | Complex domain floating point VLIW DSP with data/program bus multiplexer and microprocessor interface A system for digital signal processing, configured as a system on chip (SoC), combines a microprocessor core and digital signal processor (DSP) core with floating-point data processing capability. The DSP core can perform operations on floating-point data in a compl... | 10/14/2008 |
| 7428629 | Memory request / grant daemons in virtual nodes for moving subdivided local memory space from VN to VN in nodes of a massively parallel computer system A memory management mechanism a nodal having multiple processors in a massively parallel computer system dynamically configures nodal memory on demand. A respective variable-sized subdivision of nodal memory is associated with each processor in the node. A processor... | 09/23/2008 |
| RE40509 | Methods and apparatus for abbreviated instruction sets adaptable to configurable processor architecture An improved manifold array (ManArray) architecture addresses the problem of configurable application-spacific instruction set optimization and instruction memory reduction using an instruction abbreviation process thereby further optimizing the general ManArray arch... | 09/16/2008 |
| 7418578 | Simultaneously assigning corresponding entry in multiple queues of multi-stage entries for storing condition attributes for validating simultaneously executed conditional execution instruction groups A processor is disclosed including several features allowing the processor to simultaneously execute instructions of multiple conditional execution instruction groups. Each conditional execution instruction group includes a conditional execution instruction and a co... | 08/26/2008 |
| 7418576 | Prioritized issuing of operation dedicated execution unit tagged instructions from multiple different type threads performing different set of operations A graphics processor buffers vertex thread and pixel threads. The different types of threads issue instructions corresponding to different sets of operations. A plurality of different types of execution units are provided, each type of execution unit servicing a dif... | 08/26/2008 |
| 7415599 | Instruction operation and operand memory location determined based on preceding instruction operation and operand memory location A repeat instruction (RPT) operates on one or more operands, but the RPT instruction includes only an opcode and does not specify locations of the operand or operands. The type of operation to be performed when the RPT instruction is executed depends upon an initial... | 08/19/2008 |
| 7415595 | Data processing without processor core intervention by chain of accelerators selectively coupled by programmable interconnect network and to memory A programmable digital signal processor includes a plurality of memory units, a plurality of accelerator units and a processor core. The digital signal processor also includes a programmable network that may be configured to selectively provide connectivity between ... | 08/19/2008 |
| 7412588 | Network processor system on chip with bridge coupling protocol converting multiprocessor macro core local bus to peripheral interfaces coupled system bus A network processor includes a system-onchip (SoC) macro core and functions as a single chip protocol converter that receives packets generating according to a first protocol type and processes the packets to implement protocol conversion and generates converted pac... | 08/12/2008 |
| 7409533 | Asynchronous communication among hardware object nodes in IC with receive and send ports protocol registers using temporary register bypass select for validity information Embodiments of the invention are directed to an integrated circuit including a communication network that interconnects individual object nodes. The nodes include a receiving port and a sending port, each structured to send messages along communication pathways, whi... | 08/05/2008 |
| 7406584 | IC comprising network of microprocessors communicating data messages along asynchronous channel segments using ports including validity and accept signal registers and with split / join capability Embodiments of the invention are directed to a communication network on an integrated circuit for a number of interconnected microprocessors. The network is made from a number of sending nodes and receiving nodes each coupled by a communication channel. Individual c... | 07/29/2008 |
| 7406588 | Dynamically reconfigurable stages pipelined datapath with data valid signal controlled multiplexer A pipelined datapath with dynamically reconfigurable pipeline stages is provided, having a pipeline controller which generates clock signals and selects signals based on a system clock and a valid data signal to control each of the registers and each of the multiple... | 07/29/2008 |
| 7404181 | Switching to original code comparison of modifiable code for translated code validity when frequency of detecting memory overwrites exceeds threshold A method of translating instructions from a target instruction set to a host instruction set. In one embodiment, a plurality of first target instructions is translated into a plurality of first host instructions. After the translation, it is determined whether the p... | 07/22/2008 |
| 7401209 | Limiting entries searched in load reorder queue to between two pointers for match with executing load instruction A method for reducing the number of load instructions in the load reorder queue (LRQ) that are searched when a load instruction is executed by a processor, including dispatching the load instructions; inserting the load instructions in the LRQ in program order; clea... | 07/15/2008 |
| 7398378 | Allocating lower priority interrupt for processing to slave processor via master processor currently processing higher priority interrupt through special interrupt among processors In a multi-processor system with a master-slave configuration, interrupts are efficiently allocated and processed between the processors to improve a real-time performance. A master processor (MP) provided with an operating system (OS), a slave processor (SP), an in... | 07/08/2008 |
| 7392369 | Decomposing architectural operation into speculative and architectural micro-operations for speculative execution of others and for violation check Embodiments include various methods, apparatuses, and systems in which a processor includes an out of order issue engine and an in-order execution pipeline. For some embodiments, the issue engine may be remote from the execution pipeline and execution resources may ... | 06/24/2008 |
| 7392368 | Cross multiply and add instruction and multiply and subtract instruction SIMD execution on real and imaginary components of a plurality of complex data elements Methods and apparatus for calculating Single-Instruction-Multiple-Data (SIMD) complex arithmetic. A coprocessor instruction has a format identifying a multiply and subtract instruction to generate real components for complex multiplication of first operand complex d... | 06/24/2008 |
| 7392367 | Command ordering among commands in multiple queues using hold-off vector generated from in-use vector and queue dependency scorecard A method, apparatus, system, and signal-bearing medium that in various embodiments determine whether to execute a command in a queue or whether to wait until another command or commands completed. The determination is based on a combination of an in-use vector and a... | 06/24/2008 |
| 7380105 | Prediction based instruction steering to wide or narrow integer cluster and narrow address generation A method and apparatus for improving the operation of a computer processor by utilizing an asymmetric clustered processor architecture are disclosed. The asymmetric clustered processor apparatus includes a narrow cluster, a wide cluster, a steering logic utilizing a... | 05/27/2008 |
| 7380111 | Out-of-order processing with predicate prediction and validation with correct RMW partial write new predicate register values A method for processing registers in an out-of-order processor. A predicate in an instruction is predicted. An architecturally correct value is then computed using a read-modify-write operation. The predicted value is compared to the architecturally correct value. T... | 05/27/2008 |
| 7380102 | Communication link control among inter-coupled multiple processing units in a node to respective units in another node for request broadcasting and combined response A data processing system includes a first processing node and a second processing node. The first processing node includes a plurality of first processing units coupled to each other for communication, and the second processing node includes a plurality of second pr... | 05/27/2008 |
| 7373488 | Processing for associated data size saturation flag history stored in SIMD coprocessor register using mask and test values A method and apparatus for calculation and storage of Single-Instruction-Multiple-Data (SIMD) saturation history information. A first coprocessor instruction has a first format identifying a saturating operation, a first source having packed data elements and a seco... | 05/13/2008 |
| 7370184 | Shifter for alignment with bit formatter gating bits from shifted operand, shifted carry operand and most significant bit An apparatus for shifting data is disclosed. The apparatus includes a shifter, a register, and a shift post processor. The shifter shifts an operand according to an offset parameter, thereby generating a shifted operand. The register is coupled to the shift post pro... | 05/06/2008 |
| 7366878 | Scheduling instructions from multi-thread instruction buffer based on phase boundary qualifying rule for phases of math and data access operations with better caching A processor buffers asynchronous threads. Current instructions requiring operations provided by a plurality of execution units are divided into phases, each phase having at least one math operation and at least one texture cache access operation. Instructions within... | 04/29/2008 |
| 7363478 | Retrieving multi-byte vector elements from byte indexed table using replicated and consecutive number added indices for each element index A lookup operation is carried out on a data table by logically dividing the data table into a number of smaller sets of data that can be indexed with a single byte of data. Each set of data consists of two vectors, which constitute the operands for a permute instruc... | 04/22/2008 |
| 7356676 | Extracting aligned data from two source registers without shifting by executing coprocessor instruction with mode bit for deriving offset from immediate or register A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a copr... | 04/08/2008 |
| 7353500 | Suppressing execution of monitoring measurement program pointed to by inserted branch after threshold number of coverage to reduce instruction testing overhead In a method for testing a program, repeated measurement on branches that are frequently taken is prevented, thereby avoiding unnecessary overhead. An information processing device includes a coverage measurement control program for determining whether the number of ... | 04/01/2008 |
| 7353362 | Multiprocessor subsystem in SoC with bridge between processor clusters interconnetion and SoC system bus A System-on-Chip (SoC) component comprising a single independent multiprocessor subsystem core including a plurality of multiple processors, each multiple processor having a local memory associated therewith forming a processor cluster; and a switch fabric means con... | 04/01/2008 |
| 7350062 | Predicted return address from return stack entry designated by computation unit with multiple inputs including return hit flag and re-fetch signal An information processing apparatus is capable of speculatively performing an execution, such as a pipeline/superscalar/out-of-order execution and equipped with a branch prediction mechanism (a branch history). The information processing apparatus, in order to proce... | 03/25/2008 |
| 7350057 | Scalar result producing method in vector/scalar system by vector unit from vector results according to modifier in vector instruction Described herein is a method and system for executing instructions. The system comprises a scalar unit for executing scalar instructions each defining a single value pair; a vector unit for executing vector instructions each defining multiple value pairs; and an ins... | 03/25/2008 |
| 7350061 | Assigning free register to unmaterialized predicate in inverse predicate expression obtained for branch reversal in predicated execution system Described is a method that identifies a predicate expression representing conditions in predicated assembly language instructions that determine a direction of a conditional branch instruction. The predicate expression is employed to enable a transformation to be ma... | 03/25/2008 |
| 7346761 | Alu with auxiliary units for pre and post processing of operands and immediate value within same instruction cycle An arithmetic and logic device as an integral part of a processing unit is provided to achieve code size and overhead reduction. The arithmetic and logic device contains several auxiliary computing units, each of which is capable of simple arithmetic and logical ope... | 03/18/2008 |
| 7343475 | Supplying halt signal to data processing unit from integer unit upon single unit format instruction in system capable of executing double unit format instruction A processor including an integer processing unit and a data processing unit. The processor can be operated by a first instruction format or a second instruction format. The first instruction format includes only an instruction for the integer processing unit, and is... | 03/11/2008 |
| 7340586 | Data transfer for debugging in data driven type processor processing data packet with data flow program including transfer control bit setting instruction A data-driven type information processor includes a ifinction processor manipulating contents in a data packet, a program storage unit storing a data flow program used by the function processor, and a branch unit controlling data flow whether to allow flow of a data... | 03/04/2008 |
