| Patent No. | Patent Title: |
| 7664936 | Prioritizing thread selection partly based on stall likelihood pr... |
| 7464253 | Tracking multiple dependent instructions with instruction queue p... |
| 7454595 | Distributed processor allocation for launching applications in a ... |
| 7454593 | Row and column enable signal activation of processing array eleme... |
| 7451293 | Array of Boolean logic controlled processing elements with concur... |
| 7451298 | Processing exceptions from 64-bit application program executing i... |
| 7441099 | Configurable SIMD processor instruction specifying index to LUT s... |
| 7437540 | Complex domain floating point VLIW DSP with data/program bus mult... |
| 7428629 | Memory request / grant daemons in virtual nodes for moving subdiv... |
| RE40509 | Methods and apparatus for abbreviated instruction sets adaptable ... |
| 7418578 | Simultaneously assigning corresponding entry in multiple queues o... |
| 7418576 | Prioritized issuing of operation dedicated execution unit tagged ... |
| 7415599 | Instruction operation and operand memory location determined base... |
| 7415595 | Data processing without processor core intervention by chain of a... |
| 7412588 | Network processor system on chip with bridge coupling protocol co... |
| 7409533 | Asynchronous communication among hardware object nodes in IC with... |
| 7406584 | IC comprising network of microprocessors communicating data messa... |
| 7406588 | Dynamically reconfigurable stages pipelined datapath with data va... |
| 7404181 | Switching to original code comparison of modifiable code for tran... |
| 7401209 | Limiting entries searched in load reorder queue to between two po... |
| 7398378 | Allocating lower priority interrupt for processing to slave proce... |
| 7392369 | Decomposing architectural operation into speculative and architec... |
| 7392368 | Cross multiply and add instruction and multiply and subtract inst... |
| 7392367 | Command ordering among commands in multiple queues using hold-off... |
| 7380105 | Prediction based instruction steering to wide or narrow integer c... |
| 7380111 | Out-of-order processing with predicate prediction and validation ... |
| 7380102 | Communication link control among inter-coupled multiple processin... |
| 7373488 | Processing for associated data size saturation flag history store... |
| 7370184 | Shifter for alignment with bit formatter gating bits from shifted... |
| 7366878 | Scheduling instructions from multi-thread instruction buffer base... |
| 7363478 | Retrieving multi-byte vector elements from byte indexed table usi... |
| 7356676 | Extracting aligned data from two source registers without shiftin... |
| 7353500 | Suppressing execution of monitoring measurement program pointed t... |
| 7353362 | Multiprocessor subsystem in SoC with bridge between processor clu... |
| 7350062 | Predicted return address from return stack entry designated by co... |
| 7350057 | Scalar result producing method in vector/scalar system by vector ... |
| 7350061 | Assigning free register to unmaterialized predicate in inverse pr... |
| 7346761 | Alu with auxiliary units for pre and post processing of operands ... |
| 7343475 | Supplying halt signal to data processing unit from integer unit u... |
| 7340586 | Data transfer for debugging in data driven type processor process... |
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