| Patent No. | Patent Title: |
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| 8019974 | Pipeline processor with write control and validity flags for cont... |
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| 7996661 | Loop processing counter with automatic start time set or trigger ... |
| 7984267 | Message passing module in hybrid computing system starting and se... |
| 7979672 | Multi-core processors for 3D array transposition by logically ret... |
| 7979674 | Re-executing launcher program upon termination of launched progra... |
| 7975126 | Reconfiguration of execution path upon verification of extension ... |
| 7971033 | Limiting entries in load issued premature part of load reorder qu... |
| 7966476 | Determining length of instruction with escape and addressing form... |
| 7966482 | Interleaving saturated lower half of data elements from two sourc... |
| 7966478 | Limiting entries in load reorder queue searched for snoop check t... |
| 7962730 | Replaying memory operation assigned a load/store buffer entry occ... |
| 7962729 | Dynamic runtime range checking of different types on a register u... |
| 7958341 | Processing stream instruction in IC of mesh connected matrix of p... |
| 7949862 | Branch prediction table storing addresses with compressed high or... |
| 7949855 | Scheduler in multi-threaded processor prioritizing instructions p... |
| 7945766 | Conditional execution of floating point store instruction by simu... |
| 7941644 | Simultaneous multi-thread instructions issue to execution units w... |
| 7941637 | Groups of serially coupled processor cores propagating memory wri... |
| 7930519 | Processor with coprocessor interfacing functional unit for forwar... |
| 7925870 | Return target address prediction by moving entry pointer to retur... |
| 7925861 | Plural SIMD arrays processing threads fetched in parallel and pri... |
| 7925862 | Coprocessor forwarding load and store instructions with displacem... |
| 7917734 | Determining length of instruction with multiple byte escape code ... |
| 7917729 | System on chip IC with subsystem of multiple processing cores swi... |
| 7917730 | Processor chip with multiple computing elements and external i/o ... |
| 7908603 | Intelligent memory with multitask controller and memory partition... |
| 7904891 | Checking for instruction invariance to execute previously obtaine... |
| 7900014 | Memory request/grant daemons in virtual nodes for moving subdivid... |
| 7900025 | Floating point only SIMD instruction set architecture including c... |
| 7886134 | Loop iteration prediction by supplying pseudo branch instruction ... |
| 7877574 | Relay node communication interface transmitting update packet to ... |
| 7873816 | Pre-loading context states by inactive hardware thread in advance... |
| 7870366 | Chained operation of functional components with DONE and GO regis... |
| 7870365 | Matrix of processors with data stream instruction execution pipel... |
| 7865696 | Interface including task page mechanism with index register betwe... |
| 7865650 | Processor with coherent bus controller at perpendicularly interse... |
| 7865693 | Aligning precision converted vector data using mask indicating of... |
| 7861072 | Throwing one selected representative exception among aggregated m... |
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