| Patent No. | Patent Title: |
| 5721862 | Enhanced DRAM with single row SRAM cache for all device read oper... |
| 5712970 | Method and apparatus for reliably storing data to be written to a... |
| 5701436 | Information processing apparatus including synchronous storage ha... |
| 5687340 | Reduced area floating point processor control logic utilizing a d... |
| 5682496 | Filtered serial event controlled command port for memory |
| 5666512 | Disk array having hot spare resources and methods for using hot s... |
| 5666556 | Method and apparatus for redirecting register access requests whe... |
| 5664147 | System and method that progressively prefetches additional lines ... |
| 5664154 | M/A for optimizing retry time upon cache-miss by selecting a dela... |
| 5661800 | Method and manufacture for preventing unauthorized use by judging... |
| 5659695 | Method and apparatus utilizing simultaneous memory reads for incr... |
| 5652906 | Data driven processor with improved initialization functions beca... |
| 5651135 | Multi-way set associative cache system in which the number of lin... |
| 5651133 | Methods for avoiding over-commitment of virtual capacity in a red... |
| 5640535 | Library apparatus for duplicating disks and then sorting them to ... |
| 5640602 | Transferring digital data in units of 2 bytes to increase utiliza... |
| 5634099 | Direct memory access unit for transferring data between processor... |
| 5634110 | Cache coherency using flexible directory bit vectors |
| 5634106 | Power saving system and method for refreshing a computer memory b... |
| 5615352 | Methods for adding storage disks to a hierarchic disk array while... |
| 5566318 | Circuit with a single address register that augments a memory con... |
| 5555399 | Dynamic idle list size processing in a virtual memory management ... |
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