| Patent No. | Patent Title: |
| 6380762 | Multi-level programmable voltage control and output buffer with s... |
| 6340898 | Method and system for switching between a totem-pole drive mode a... |
| 6236228 | Structure and method of repair of integrated circuits |
| 6232793 | Switched backgate bias for FET |
| 6222391 | Semiconductor integrated circuit |
| 6215328 | Buffer circuit with small delay |
| 6208162 | Technique for preconditioning I/Os during reconfiguration |
| 6201409 | High performance product term based carry chain scheme |
| 6191618 | Contention-free, low clock load domino circuit topology |
| 6191616 | Low power, high speed level shifter |
| 6191611 | Driver circuitry for programmable logic devices with hierarchical... |
| 6191608 | Techniques for programming programmable logic array devices |
| 6188338 | Coding apparatus, decoding apparatus and methods applied thereto |
| 6188236 | Arrangement and method relating to digital information in superco... |
| 6184711 | Low impact signal buffering in integrated circuits |
| 6184702 | Crosstalk prevention circuit |
| 6184705 | Techniques for programming programmable logic array devices |
| 6184701 | Integrated circuit devices having metastability protection circui... |
| 6184704 | Design method for compensation of process variation in CMOS digit... |
| 6184710 | Programmable logic array devices with enhanced interconnectivity ... |
| 6181158 | Configuration logic to eliminate signal contention during reconfi... |
| 6181165 | Reduced voltage input/reduced voltage output tri-state buffers |
| 6181157 | Resistor mirror |
| 6177808 | Integration of bidirectional switches with programmable logic |
| 6177811 | Semiconductor integrated circuit device |
| 6175251 | Semiconductor integrated circuit device having power reduction |
| 6172531 | Low power wordline decoder circuit with minimized hold time |
| 6172532 | Gate circuit and semiconductor circuit to process low amplitude s... |
| 6172519 | Bus-hold circuit having a defined state during set-up of an in-sy... |
| 6172529 | Compound domino logic circuit having output noise elimination |
| 6169416 | Programming architecture for field programmable gate array |
| 6169420 | Output buffer |
| 6169419 | Method and apparatus for reducing standby leakage current using a... |
| 6160417 | Termination circuits and related output buffers |
| 6157206 | On-chip termination |
| 6154062 | Semiconductor integrated circuits with power reduction mechanism |
| 6154047 | Bus configuration and input/output buffer |
| 6154055 | Programmable logic array integrated circuit devices |
| 6150848 | Two-phase dynamic logic circuits for gallium arsenide complementa... |
| 6147508 | Power consumption control mechanism and method therefor |