U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

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Examiner: Santamauro, Jon


Primary examiner statistics: 409 patents; average approval time: 827 days
Assistant examiner statistics: 260 patents; average approval time: 660 days

Patents as Primary Examiner (view all)

Patent No. Patent Title:
6380762 Multi-level programmable voltage control and output buffer with s...
6340898 Method and system for switching between a totem-pole drive mode a...
6236228 Structure and method of repair of integrated circuits
6232793 Switched backgate bias for FET
6222391 Semiconductor integrated circuit
6215328 Buffer circuit with small delay
6208162 Technique for preconditioning I/Os during reconfiguration
6201409 High performance product term based carry chain scheme
6191618 Contention-free, low clock load domino circuit topology
6191616 Low power, high speed level shifter
6191611 Driver circuitry for programmable logic devices with hierarchical...
6191608 Techniques for programming programmable logic array devices
6188338 Coding apparatus, decoding apparatus and methods applied thereto
6188236 Arrangement and method relating to digital information in superco...
6184711 Low impact signal buffering in integrated circuits
6184702 Crosstalk prevention circuit
6184705 Techniques for programming programmable logic array devices
6184701 Integrated circuit devices having metastability protection circui...
6184704 Design method for compensation of process variation in CMOS digit...
6184710 Programmable logic array devices with enhanced interconnectivity ...
6181158 Configuration logic to eliminate signal contention during reconfi...
6181165 Reduced voltage input/reduced voltage output tri-state buffers
6181157 Resistor mirror
6177808 Integration of bidirectional switches with programmable logic
6177811 Semiconductor integrated circuit device
6175251 Semiconductor integrated circuit device having power reduction
6172531 Low power wordline decoder circuit with minimized hold time
6172532 Gate circuit and semiconductor circuit to process low amplitude s...
6172519 Bus-hold circuit having a defined state during set-up of an in-sy...
6172529 Compound domino logic circuit having output noise elimination
6169416 Programming architecture for field programmable gate array
6169420 Output buffer
6169419 Method and apparatus for reducing standby leakage current using a...
6160417 Termination circuits and related output buffers
6157206 On-chip termination
6154062 Semiconductor integrated circuits with power reduction mechanism
6154047 Bus configuration and input/output buffer
6154055 Programmable logic array integrated circuit devices
6150848 Two-phase dynamic logic circuits for gallium arsenide complementa...
6147508 Power consumption control mechanism and method therefor

Patents as Assistant Examiner (view all)

Patent No. Patent Title:
5821770 Option decoding with on-chip electrical fuses
5808478 Digitally controlled output buffer to incrementally match line im...
5804987 LSI chip having programmable buffer circuit
5777491 High-performance differential cascode voltage switch with pass ga...
5764078 Family of multiple segmented programmable logic blocks interconne...
5742179 High speed programmable logic architecture
5742180 Dynamically programmable gate array with multiple contexts
5734272 Differential stage logic circuit
5723988 CMOS with parasitic bipolar transistor
5721498 Block segmentation of configuration lines for fault tolerant ...
5717346 Low skew multiplexer network and programmable array clock/reset ...
5717344 PLA late signal circuitry using a specialized gap cell and PLA la...
5708374 Self-timed control circuit for self-resetting logic circuitry
5708373 Boost circuit
5705938 Programmable switch for FPGA input/output signals
5705941 Output driver for use in semiconductor integrated circuit
5703498 Programmable array clock/reset resource
5703496 Method and apparatus for limiting the slew rate of output drivers...
5704014 Voltage-current conversion circuit employing MOS transistor cells...
5701090 Data output circuit with reduced output noise
5701095 High speed, low noise CMOS multiplexer with precharge
5698993 CMOS level shifting circuit
5698997 Resonant tunneling diode structures for functionally complete low...
5698994 Data output circuit, intermediate potential setting circuit, and ...
5698991 Bus driver
5696456 Enhanced low voltage TTL interface
5691652 Completion detection as a means for improving alpha soft-error re...
5682105 Bonding option circuit having no pass-through current
5680063 Bi-directional voltage translator
5677641 Gate circuit and semiconductor circuit to process low amplitude s...
5672985 Programmable logic array integrated circuits with carry and/or ca...
5670900 Mask decoder circuit optimized for data path
5670894 Semiconductor device having output signal control circuit
5668485 Row decoder with level translator
5666069 Data output stage incorporating an inverting operational amplifie...
5666067 Voltage compensating CMOS input buffer circuit
5663663 Mixed voltage interface converter
5661414 Output circuit for use in a semiconductor integrated circuit
5661416 Interface circuit and interface-network system using the same
5659258 Level shifter circuit
 
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