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| Number | Title | Issue Date |
| 6035126 | Data pipeline system and data encoding method A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and... | 03/07/2000 |
| 5850518 | Access-method-independent exchange The present invention provides a virtual network, sitting "above" the physical connectivity and thereby providing the administrative controls necessary to link various communication devices via an Access-Method-Independent Exchange. In this sense, the ... | 12/15/1998 |
| 5838942 | Panic trap system and method A panic trap system recovers from inaccurate results produced from out of order execution of instructions in a processor. The panic trap system includes a fetch mechanism (IFETCH) that fetches instructions from an instruction cache. Two queues receive the... | 11/17/1998 |
| 5835714 | Method and apparatus for reservation of data buses between multiple storage control elements A data bus reservation system controls data transfer between storage control elements (SCEs) in a multi-processor system. Each SCE is assigned a default bidirectional (BIDI) data bus for transfer of data. If a request for data transfer is made and the def... | 11/10/1998 |
| 5835740 | Data pipeline system and data encoding method A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and... | 11/10/1998 |
| 5828894 | Array processor having grouping of SIMD pickets Array processors are made by assembling individual microcomputer elements into an array. Larger arrays are called massively parallel processors. Some can operate in SIMD, while others can operate in MIMD, or SIMD and MIMD in special configurations. In a S... | 10/27/1998 |
| 5815723 | Picket autonomy on a SIMD machine A parallel array computer provides an array of processor memory elements interconnected for transfer of data and instructions between processor memory elements. Each of the processing elements has a processor coupled with a local memory. An array controll... | 09/29/1998 |
| 5806049 | Data processing system for global assessment of investment opportunity and cost A data processing system for determining a matrix of optimal investment portfolios based on globally accessed investment return and risk criteria. The system creates a global defined database of investment assets and investors. Asset and investor characte... | 09/08/1998 |
| 5805914 | Data pipeline system and data encoding method A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and... | 09/08/1998 |
| 5799181 | Bossless architecture and digital cell technology for computer programs A bossless computer program architecture in which each program module is hierarchically equal is used to develop complicated software applications. Each program module is associated with a parameter file. The characteristics and operation of the program m... | 08/25/1998 |
| 5797028 | Computer system having an improved digital and analog configuration A computer system including separate digital and analog system chips which provides increased performance over current computer architectures. The computer system of the present invention includes a digital system chip which performs various digital funct... | 08/18/1998 |
| 5790881 | Computer system including coprocessor devices simulating memory interfaces A method and system for coupling a coprocessor to a master device, in which the coprocessor emulates an memory interface to the master device, like that of a memory device. The coprocessor is coupled to a memory bus and receives memory accesses directed t... | 08/04/1998 |
| 5790805 | Distributed timer synchronization A method, apparatus, and article of manufacture for establishing an unlimited number of independent, client-based timers, synchronized with a timer kept on a central server, is disclosed. After forming a client-server connection, a client sends a synchron... | 08/04/1998 |
| 5784630 | Method and apparatus for processing data in multiple modes in accordance with parallelism of program by using cache memory A data processing system having flexibility coping with parallelism of a program comprises a plurality of processor elements for executing instructions, a main memory shared by the plurality of processor elements, and a plurality of parallel operation con... | 07/21/1998 |
| 5784631 | Huffman decoder A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and... | 07/21/1998 |
| 5778241 | Space vector data path A space vector data path for integrating SIMD scheme into a general-purpose programmable processor. The programmable processor uses a mode field in each instruction to specify, for each instruction, whether an operand is processed in either one of vector ... | 07/07/1998 |
| 5768608 | Data processing apparatus and method for making same A data processing apparatus capable of receiving a CPU of different data bus widths is disclosed. Terminals for the lower 32 bits of a 64-bit data bus and terminals for upper 32 bits of the 64-bit data bus are provided opposing to one another at a connect... | 06/16/1998 |
| 5764910 | Method and apparatus for encoding and using network resource locators Access to data resources on data communications networks is simplified by encoding data resource specifiers into a compressed form which can be stored in a service provider's telephone equipment and transmitted to a user. The service provider stores infor... | 06/09/1998 |
| 5761691 | Linearly addressable microprocessor cache A microprocessor conforming to the X86 architecture is disclosed which includes a linearly addressable cache, thus allowing the cache to be quickly accessed by an external bus while allowing fast translation to a logical address for operation with functio... | 06/02/1998 |
| 5754789 | Apparatus and method for controlling point-to-point interconnect communications between nodes An interconnect controller for use in an arbitrary topology collection of nodes in a network suitable for use for both data sharing and distributed computing. The interconnect controller provides four (4) serial ports and two (2) parallel ports for commun... | 05/19/1998 |
| 5754752 | End-to-end session recovery A session recovery mechanism that permits the recovery of a session with a minimal delay to a user and with minimal data loss. When the client/server communications protocol process, such as TCP/IP process, issues an error message to a server and a client... | 05/19/1998 |
| 5752030 | Program execution control in parallel processor system for parallel execution of plural jobs by selected number of processors In submitting each job in a parallel processing system provided with a plurality of processors, execution conditions such as a requested minimum processor number, an upper limit used processor number and a requested execution time are designated for each ... | 05/12/1998 |
| 5752259 | Instruction cache configured to provide instructions to a microprocessor having a clock cycle time less than a cache access time of said instruction cache An apparatus including a banked instruction cache and a branch prediction unit is provided. The banked instruction cache allows multiple instruction fetch addresses (comprising consecutive instruction blocks from the predicted instruction stream being exe... | 05/12/1998 |
| 5751951 | Network interface A packet based data transmission system includes a flexible optimized nonocking transmit interface that incorporates optimized buffer modes, dynamic and static chaining, streaming and the utilization of small packet formats. Static chaining refers to con... | 05/12/1998 |
| 5748900 | Adaptive congestion control mechanism for modular computer networks A congestion control mechanism for a node of a modular computer network system. The mechanism includes registers for maintaining the number of undelivered requests and unanswered requests for the node and registers for the maximum number of such undeliver... | 05/05/1998 |
| 5748915 | Transmission method of changing protocol and data processing apparatus using this method As a method for transferring data between a first data processing apparatus and a second data processing apparatus connected thereto attachably and detachably, there is provided a transmission method of changing protocol having a step for transmitting a f... | 05/05/1998 |
| 5745884 | System and method for billing data grade network use on a per connection basis A system and method in which remote users may be billed, on a per connection basis, for universal data grade access to their home office servers. Portable device 101 is carried by a transient remote user within wireless range of an Access Point (AP) 110 d... | 04/28/1998 |
| 5742761 | Apparatus for adapting message protocols for a switch network and a bus A conversion apparatus that converts and adapts standard processor bus protocol and architecture, such as the MicroChannel (IBM Trademark) bus, to more progressive switch interconnection protocol and architecture. Existing bus-based architecture is extend... | 04/21/1998 |
| 5740460 | Arrangement for processing packetized data An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both con... | 04/14/1998 |
| 5737630 | Communication device for synchronized serial communication In order to shorten time needed for communication and alleviate the processing load of the handshake procedure, a master CPU and a slave CPU perform an exchange of data utilizing a first data line and a second data line. A key word is entered in a communi... | 04/07/1998 |
| 5737615 | Microprocessor power control in a multiprocessor computer system A power down control mechanism for multiprocessor computer systems. A power down register is maintained for providing a power down control signal to the multiple processing units in the multiprocessing system. Individual processing units can be selectivel... | 04/07/1998 |
| 5737628 | Multiprocessor computer system with interleaved processing element nodes A multidimensional interconnection and routing apparatus for a parallel processing computer connects together processing elements in a three-dimensional structure. The interconnection and routing apparatus includes a plurality of processing element nodes.... | 04/07/1998 |
| 5734826 | Variable cyclic redundancy coding method and apparatus for use in a multistage network An error checking method and apparatus for appending a variable number of redundancy coding information at the end of each data message or packet transmitted over a multi-stage network for the purpose of protecting the data by using an error detecting cod... | 03/31/1998 |
| 5729688 | Network element managing system A network element managing system includes a management control section for maintaining and managing network elements such as an exchange or a telecommunication line and a communication control section for controlling the communication processing of the n... | 03/17/1998 |
| 5727208 | Method and apparatus for configuration of processor operating parameters A configuration system including a processor having memory for storing operating parameters and configuration logic for retrieving the operating parameters and configuring a computer system to achieve a desired performance level. The configuration logic p... | 03/10/1998 |
| 5727172 | Method and apparatus for performing atomic accesses in a data processing system A method and apparatus for performing atomic accesses in a data processing system (10). In one embodiment, a small number of control signals (e.g. 100-102; or 103-104; or 105-108 from FIG. 3 ) are used to provide information regarding the status of reserv... | 03/10/1998 |
| 5727227 | Interrupt coprocessor configured to process interrupts in a computer system A computer system employing an interrupt coprocessor is provided. The interrupt coprocessor is signaled by an interrupt controller to service a particular interrupt request. The interrupt coprocessor may include limited functionality, such that if a parti... | 03/10/1998 |
| 5727226 | Method and apparatus for modulation of multi-dimensional data in holographic storage A modulator apparatus for modulating arrays of input data Vin to be stored in a holographic recording medium is disclosed wherein the final output data array Vout has frequent transitions from light to dark and from dark to light in ... | 03/10/1998 |
| 5721942 | Personal information display system for serving large capacities of general information to user-designated stations at user-designated times A personal information display system is provided with a portable information display device for reading information to be used from a storage medium, a communication network for transmission of information, input/output apparatus for input/output of info... | 02/24/1998 |
| 5715392 | Method for managing visual type compatibility in a conferencing network system having heterogeneous hardware A conference enabled X windows networking system using a method for determining the best match available for a conference owner's visual type is disclosed. In the system, the enabler determines if the visual type detected in the X protocol stream is the c... | 02/03/1998 |
