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...that the first rickshaw was invented in 1869 by an American Baptist minister, the Rev. E. Jonathan Scobie, to transport his invalid wife around the streets of Yokohama?
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| Number | Title | Issue Date |
| 5832215 | Data gathering/scattering system for a plurality of processors in a parallel computer In a data gathering/scattering system having a data gathering system and a data scattering system in a parallel computer constituted by a plurality of processors connected in parallel through a common bus or hierarchical common buses, the data gathering/s... | 11/03/1998 |
| 5822775 | Efficient data processing method for coefficient data in a digital dignal, processor A coefficient data transfer processing method for a digital signal processor which has a coefficient address pointer independent of a program counter, whereby a processing program and coefficient data are transferred and supplied from a microcomputer dete... | 10/13/1998 |
| 5784632 | Parallel diagonal-fold array processor A massively parallel processor apparatus having an instruction set architecture for each of the N2 the PEs of the structure. The apparatus which we prefer will have a PE structure consisting of PEs that contain instruction and data storage unit... | 07/21/1998 |
| 5784604 | Method and system for reduced run-time delay during conditional branch execution in pipelined processor systems utilizing selectively delayed sequential instruction purging A method and system are disclosed for reducing run-time delay during conditional branch instruction execution in a pipelined processor system. A series of queued sequential instructions and conditional branch instructions are processed wherein each condit... | 07/21/1998 |
| 5781801 | Method and apparatus for receive buffer management in multi-sender communication systems A receive buffer management system associates a virtual buffer pool with each node communicating with a receiver and creates an actual buffer pool for use by all nodes, with a "low-water-mark" indicating buffers are running out and a "high-water-mark" ind... | 07/14/1998 |
| 5761664 | Hierarchical data model for design automation A computer model for facilitating computer assisted design includes data structures which are flexibly organized by storing of information in accordance with entities or simulations thereof (including symbolic layer entities, area entities, area spec enti... | 06/02/1998 |
| 5752060 | File access scheme in distributed data processing system A file access scheme in a distributed data processing system for executing an access to a file in response to a file server to effect a data processing includes a device for executing an input/output processing such that each processing module unit operat... | 05/12/1998 |
| 5748976 | Mechanism for maintaining data coherency in a branch history instruction cache A system for maintaining the integrity of data stored in a branch prediction mechanism such as a branch target buffer (BTB). Upon encountering a branch instruction, a stream of target instructions is prefetched from cache memory even though the target ins... | 05/05/1998 |
| 5717946 | Data processor A data processor having a string operation instruction and a bit map operation instruction, and comprises a bus interface unit 157 which inputs/outputs data by the burst transfer function, and an integer operation unit 155 building-in a main ALU and a sub... | 02/10/1998 |
| 5710937 | Sorting apparatus A sorting apparatus is composed of sort processors connected in a pipeline fashion. Each sort processor 106 merge sorts data from the preceding sort processor and then outputs the merge sort result to the succeeding sort processor. The sort processor incl... | 01/20/1998 |
| 5708838 | Distributed processing systems having a host processor and at least one object oriented processor Distributed processing systems having a host processor and at least one object oriented processor are disclosed. An object oriented processor according to the invention has a communications interface, an intelligent message handler, and a task-specific fu... | 01/13/1998 |
| 5701412 | Telecommunications service control method in intelligent network A trigger is armed to a predetermined detection point (DP) of a basic call state model controlled for each call by a switching system so that a service control point (SCP) can be unconditionally activated. The SCP stores service control information for ea... | 12/23/1997 |
| 5685004 | Multi-segmented bus and method of operation A multi-level hierarchical bus architecture implemented with a multi-chip package and a modular shared-bus provides high bandwidth. All IC components are mounted on standardized multi-chip packages. Each multi-chip package includes bus interface chips for... | 11/04/1997 |
| 5682534 | Transparent local RPC optimization A method for managing communication between a client process and a server process in a distributed computing environment, the client process residing on a host computer that is connected to a physical network having a transport layer and a network layer. ... | 10/28/1997 |
| 5682544 | Massively parallel diagonal-fold tree array processor A massively parallel processor apparatus having an instruction set architecture for each of the N2 the PEs of the structure. The apparatus which we prefer will have a PE structure consisting of PEs that contain instruction and data storage unit... | 10/28/1997 |
| 5680636 | Document annotation and manipulation in a data processing system A data processing system is programmed to display an annotatable bit map image of a text document, a spreadsheet and the like. Annotations are superimposed on a displayed, annotatable image, under control of an annotation program, in response to an input ... | 10/21/1997 |
| 5678057 | Multi-Chip-Module (MCM) microcircuit including multiple processors and Advanced Programmable Interrupt Controller (APIC) A Multi-Chip-Module (MCM) microcircuit comprises a substrate, a plurality of integrated circuit processors mounted on the substrate, and an Advanced Programmable Interrupt Controller (APIC) system for distributing interrupts to the processors. The APIC sy... | 10/14/1997 |
| 5675360 | Information processing apparatus having a keyboard with a pointing device An information processing apparatus includes a main case body having installed thereon a key group at a key installation region thereof, a track ball and a selection switch (including a right switch and a left switch) are separately provided, respectively... | 10/07/1997 |
| 5671423 | Device for controlling the switchover of processor operation from an instantaneous status to a subsequent status Proposed is a device which makes it possible to switch several processors from an instantaneous status to a follow-on status. The device is intended in particular for memory-programmable control units, referred to as memory-programmable status control uni... | 09/23/1997 |
| 5659763 | Apparatus and method for reducing power consumption by peripheral devices by controlling the interconnection of power supplies Peripherals connected to an external bus is connected to a power source section through switching units, and a buffer circuit connected to an internal bus and the external bus is consisted of a separating unit. An internal memory and power consumption red... | 08/19/1997 |
| 5659789 | Stopclock toggle system for powering two CPUs from a regulator only sized for one CPU The present invention relates to a fault tolerant system for providing power to a multiple central processing unit computer system. Three DC-DC converters, each sized for providing power to one central processing unit, furnish power to two central process... | 08/19/1997 |
| 5655079 | Data processing system and data transmission and processing method A data transmission method is provided for a multi-computer system which has a plurality of computers mutually connected via a transmission line. The plurality of computers are divided into groups, with an address assigned to each group. Transmission data... | 08/05/1997 |
| 5652904 | Non-reconfigurable microprocessor-emulated FPGA In accordance with the present invention, a microprocessor controlled device is provided which appears to a user to be a programmable logic device. Signals are taken from and placed on external pins in the same manner as would be done with a prior art pro... | 07/29/1997 |
| 5649229 | Pipeline data processor with arithmetic/logic unit capable of performing different kinds of calculations in a pipeline stage The data processors of the present invention transfer the contents of address registers and program registers through an unused bus during the cycle of writing into registers and execute, in one cycle, a load instruction or a store instruction that requir... | 07/15/1997 |
| 5649227 | System for supporting a conversion between abstract syntax and transfer syntax The system for supporting input or reference of a data value or a structure value which is a component of a PDU (Protocol Data Unit). The abstract syntax of PDU is defined in accordance with ISO8824 (international standard ASN.1 (Abstract Syntax Notation ... | 07/15/1997 |
| 5649108 | Combined progressive and source routing control for connection-oriented communications networks In a connection-oriented communications network, a source node selects one of first and second routing mode flags and a first route to a destination node in response to a connection request, and establishes a connection to a first intermediate node locate... | 07/15/1997 |
| 5644717 | System for generating local area network operating statistics based on monitored network traffic and method therefor A system for generating operating statistics for a network interconnecting at least two stations wherein each of those stations may send and receive messages during a session is implemented in software programmed to monitor the messages on the network, as... | 07/01/1997 |
| 5644720 | Interprocess communications interface for managing transaction requests The present invention provides a method of processing transaction requests from client applications within a computer network having a plurality of client servers. Each client server has a work share and a set of attributes that including a name, an addre... | 07/01/1997 |
| 5640585 | State machine bus controller A state machine bus controller for interfacing the CPU of a micro-computer based system with memory and I/O device is described. The controller, while capable of interfacing with a bus which is synchronous in nature, can maintain synchronous handshake wit... | 06/17/1997 |
| 5640586 | Scalable parallel group partitioned diagonal-fold switching tree computing apparatus A parallel computer architecture supporting neural networks utilizing a novel method of separating a triangular array containing N processing elements on each edge into multiple smaller triangular arrays, each of dimension X and each representing a common... | 06/17/1997 |
| 5625833 | Document annotation & manipulation in a data processing system A data processing system provides annotation of a document with annotations inputted through an electronic tablet, a keyboard and an audio assembly. The annotations are entered in a modeless operation of the three input streams. Input by the tablet utiliz... | 04/29/1997 |
| 5625834 | Information processing section and system for operating a plurality of vector pipeline sets in two different modes In an information processing system of the present invention, a vector processor has a plurality of vector pipeline sets operable under control of an instruction controller. The vector pipeline sets are operable in a parallel mode or in an individual mode... | 04/29/1997 |
| 5623619 | Linearly addressable microprocessor cache A microprocessor conforming to the X86 architecture is disclosed which includes a linearly addressable cache, thus allowing the cache to be quickly accessed by an external bus while allowing fast translation to a logical address for operation with functio... | 04/22/1997 |
| 5623626 | Logical cache memory for multi-processor system A logical cache memory has a logical tag and a physical tag as address tags for comparison, and status information representing their status. Data status and block status are registered at the same entry position. When access is made using a logical addre... | 04/22/1997 |
| 5619718 | Associative memory processing method for natural language parsing and pattern recognition An associative memory processor architecture is disclosed for the fast and efficient execution of parsing algorithms for natural language processing and pattern recognition applications. The architecture consists of an associative memory unit for the stor... | 04/08/1997 |
| 5619714 | Microcomputer having an instruction decoder with a fixed area and a rewritable area When a rewriting instruction data is provided to an instruction decoder from a read only memory for a program, the instruction decoder decodes the data and provides an instruction rewriting control signal to a writing block. Thereby, the writing block rec... | 04/08/1997 |
| 5619713 | Apparatus for realigning database fields through the use of a crosspoint switch A processor functioning as a coprocessor attached to a central processing complex provides efficient execution of the functions required for database processing: sorting, merging, joining, searching and manipulating fields in a host memory system. The spe... | 04/08/1997 |
| 5615356 | Method and apparatus for interactively displaying signal information during computer simulation of an electrical circuit A computer system simulator concurrently models both processor operation and signal logic behavior and provides a high degree of user interaction and flexibility in the observation and control of signal values and memory contents during the execution of a... | 03/25/1997 |
| 5613145 | Stored string data with element data units and pointer data units in distinct subranges of values An FSM data structure is encoded by generating a transition unit of data corresponding to each transition which leads ultimately to a final state of the FSM. Information about the states is included in the transition units, so that the encoded data struct... | 03/18/1997 |
| 5606711 | Apparatus and method for providing multiple output signals from a single programming line group An apparatus (100) utilizes a shift register (107) to select which of multiple synthesizers (115, 117) is to receive programming information. This allows multiple synthesizers (115, 117) to be programmed based on input from a single programing line group ... | 02/25/1997 |
