| Patent No. | Patent Title: |
| 6460094 | Peripheral device configured to detect the type of interface to w... |
| 6453446 | Timing closure methodology |
| 6397376 | Method and apparatus for determining wiring route in circuit boar... |
| 6389577 | Analyzing CMOS circuit delay |
| 6378121 | Automatic global routing device for efficiently determining optim... |
| 6378115 | LSI manufacturing method and recording medium for storing layout ... |
| 6370676 | On-demand process sorting method and apparatus |
| 6370679 | Data hierarchy layout correction and verification method and appa... |
| 6367062 | System and method for detecting an excessive number of series-con... |
| 6367054 | Method of generating finite state data for designing a cascade de... |
| 6353918 | Interconnection routing system |
| 6353922 | Automatic generation of one dimensional data compaction commands ... |
| 6347394 | Buffering circuit embedded in an integrated circuit device module... |
| 6345381 | Method and apparatus for a logic circuit design tool |
| 6341365 | Method for automating the placement of a repeater device in an op... |
| 6341367 | Hardware realized state machine |
| 6336209 | Information processing system that processes portions of an appli... |
| 6336208 | Delay optimized mapping for programmable gate arrays with multipl... |
| 6334205 | Wavefront technology mapping |
| 6327693 | Interconnect delay driven placement and routing of an integrated ... |
| 6324642 | Method and apparatus for increasing the data rate over a parallel... |
| 6324673 | Method and apparatus for edge-endpoint-based VLSI design rule che... |
| 6324620 | Dynamic DASD data management and partitioning based on access fre... |
| 6321370 | Method of supporting arrangement of semiconductor integrated circ... |
| 6317862 | Modular preamplifier head circuit layout |
| 6314545 | Quadrature solutions for 3D capacitance extraction |
| 6314553 | Circuit synthesis and verification using relative timing |
| 6314551 | System processing unit extended with programmable logic for plura... |
| 6314544 | Characterization procedure for a voltage converter connected to a... |
| 6311316 | Designing integrated circuit gate arrays using programmable logic... |
| 6311319 | Solving line-end shortening and corner rounding problems by using... |
| 6311311 | Multiple input shift register (MISR) signatures used on architect... |
| 6308309 | Place-holding library elements for defining routing paths |
| 6301696 | Final design method of a programmable logic device that is based ... |
| 6295637 | Simulator for the post-exposure bake of chemically amplified resi... |
| 6295633 | Floor-planning technique applied to circuit design in which a cir... |
| 6295632 | System and method for detecting the output of a clock driver |
| 6292926 | Functional module model, pipelined circuit synthesis and pipeline... |
| 6289496 | Placement of input-output design objects into a programmable gate... |
| 6282695 | System and method for restructuring of logic circuitry |
Bizarre Patents 
PatentStorm News
