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| Number | Title | Issue Date |
| 7598576 | Environmentally robust passivation structures for high-voltage silicon carbide semiconductor devices An improved termination structure for high field semiconductor devices in silicon carbide is disclosed. The termination structure includes a silicon carbide-based device for high-field operation, an active region in the device, an edge termination passivation for th... | 10/06/2009 |
| 7579196 | Interconnect connecting a diffusion metal layer and a power plane metal and fabricating method thereof A giant magnetoresistance (GMR) pad on the same level of GMR memory bit layer is used as an intermediate connection for plugs between the GMR pad and an underlying diffusion metal layer. A single large power metal plug is used to connect the GMR pad and the overlyin... | 08/25/2009 |
| 7579642 | Gate-enhanced junction varactor A semiconductor junction varactor utilizes gate enhancement for enabling the varactor to achieve a high ratio of maximum capacitance to minimum capacitance. ... | 08/25/2009 |
| 7575952 | Manufacturing method of semiconductor device having organic semiconductor film A method of manufacturing a semiconductor device having an organic semiconductor film comprises a step of preparing a transparent substrate at least having an opaque gate electrode and a gate insulator thereover, a step of forming a layer containing metal-nano-parti... | 08/18/2009 |
| 7576014 | Semiconductor device and manufacturing method thereof A semiconductor device with a fuse 3a to be cut for a circuit modification, of which passivation film coating the uppermost wiring layer is formed in a two-layer structure including a first insulating film 11 with high filling capability and a s... | 08/18/2009 |
| 7569400 | Ferroelectric film, method of manufacturing ferroelectric film, ferroelectric capacitor, and ferroelectric memory A ferroelectric film having a ferroelectric shown by a general formula (Pb1-dBid)(B1-aXa)O3, B including at least one of Zr and Ti, X including at least one of Nb and Ta, “a” being in a range of “0.05≦a... | 08/04/2009 |
| 7569483 | Methods of forming metal silicide layers by annealing metal layers using inert heat transferring gases established in a convection apparatus Methods of forming metal silicide layers include a convection-based annealing step to convert a metal layer into a metal silicide layer. These methods may include forming a silicon layer on a substrate and forming a metal layer (e.g., nickel layer) in direct contact... | 08/04/2009 |
| 7550398 | Semiconductor device and method of fabricating the same A semiconductor device includes a silicon nitride (SiN) film provided on a crystal surface of a nitride semiconductor, the SiN film having a hydrogen content equal to or smaller than 15 percent. ... | 06/23/2009 |
| 7550850 | Semiconductor device A semiconductor chip 100 includes a logic unit and an analog unit 153. Furthermore, the semiconductor chip 100 includes a silicon substrate 101; a first insulating film 123 to a sixth insulating film 143 formed on the silico... | 06/23/2009 |
| 7547558 | Method for manufacturing semiconductor device An Al2O3 film for covering a ferroelectric capacitor is formed by a sputtering process. The thickness of the Al2O3 film is preferably optimized according to amount of remanent polarization and fatigue tolerance required fo... | 06/16/2009 |
| 7547598 | Method for fabricating capacitor in semiconductor device A method for fabricating a capacitor in a semiconductor device includes forming a first insulation layer over a substrate, forming storage node contact plugs in the first insulation layer, contacting predetermined portions of the substrate, forming a second insulati... | 06/16/2009 |
| 7538029 | Method of room temperature growth of SiOon silicide as an etch stop layer for metal contact open of semiconductor devices Silicide is protected during MC RIE etch by first forming an oxide film over the silicide and, after performing MC RIE etch, etching the oxide film. The oxide film is formed from a film of alloyed metal-silicon (M-Si) on the layer of silicide, then wet etching the m... | 05/26/2009 |
| 7538035 | Lapping of gold pads in a liquid medium for work hardening the surface of the pads A method for work hardening gold contact pads is disclosed. The method includes providing gold contact pads, providing lapping pads, and placing the lapping pads in contact with the gold contact pads to create a contact interface. A liquid medium is then applied to ... | 05/26/2009 |
| 7527987 | Fast localization of electrical failures on an integrated circuit system and method Fast localization of electrically measured defects of integrated circuits includes providing information for fabricating a test chip having test structures configured for parallel electrical testing. The test structures on the test chip are electrically tested emplo... | 05/05/2009 |
| 7525122 | Passivation of wide band-gap based semiconductor devices with hydrogen-free sputtered nitrides A passivated semiconductor structure and associated method are disclosed. The structure includes a silicon carbide substrate or layer; an oxidation layer on the silicon carbide substrate for lowering the interface density between the silicon carbide substrate and th... | 04/28/2009 |
| 7507640 | Method for producing silicon wafer A method for producing a silicon wafer, comprising performing an activation of metallic impurities by irradiating laser light on the metallic impurities constituting contaminants in the silicon wafer, changing the electric charge of the contaminants, and activating ... | 03/24/2009 |
| 7494904 | Plasma-assisted doping Methods and apparatus are provided for igniting, modulating, and sustaining a plasma for various doping processes. In one embodiment, a substrate (250) can be doped by forming a plasma (610) in a cavity (285) by subjecting a gas to an amount of ... | 02/24/2009 |
| 7495280 | MOS devices with corner spacers A MOS device having corner spacers and a method for forming the same are provided. The method includes forming a gate structure overlying a substrate, forming a first dielectric layer over the gate structure and the substrate, forming a second dielectric layer on th... | 02/24/2009 |
| 7491588 | Method and structure for buried circuits and devices A method is provided in which for fabricating a complementary metal oxide semiconductor (CMOS) circuit on a semiconductor-on-insulator (SOI) substrate. A plurality of field effect transistors (FETs) are formed, each having a channel region disposed in a common devic... | 02/17/2009 |
| 7488682 | High-density 3-dimensional resistors Interconnect, i.e., BEOL structures comprising at least one thin film resistor that is located at the same level as that of a neighboring conductive interconnect are provided. The present invention also provides a method of fabricating such interconnect structures u... | 02/10/2009 |
| 7488643 | MIM capacitor and method of making same A MIM capacitor device and method of making the device. The device includes an upper plate comprising one or more electrically conductive layers, the upper plate having a top surface, a bottom surface and sidewalls; a spreader plate comprising one or more electrical... | 02/10/2009 |
| 7482691 | Semiconductor device and method for fabricating the same A semiconductor device and a method of fabricating a semiconductor device is provided. The semiconductor device can include a semiconductor substrate; an interlayer dielectric layer having a damascene pattern formed on the semiconductor substrate; a diffusion barrie... | 01/27/2009 |
| 7476625 | Method for fabricating semiconductor device Disclosed is a method for fabricating a semiconductor device. The method includes: forming a first inter-layer insulation layer on a substrate provided with a plurality of cell contact plugs; selectively etching the first inter-layer insulation layer to form a plura... | 01/13/2009 |
| 7470609 | Semiconductor device and method for manufacturing the same A semiconductor device including a multilevel wiring with a small interwiring capacitance is provided by comprising a wiring, a conductive film formed on an upper surface of the wiring to prevent diffusion of a wiring material, and an insulating film which is consti... | 12/30/2008 |
| 7470632 | Method of depositing a silicon dioxide comprising layer doped with at least one of P, B and Ge A substrate is positioned within a deposition chamber. At least two gaseous precursors are fed to the chamber which collectively comprise silicon, an oxidizer comprising oxygen and dopant which become part of the deposited doped silicon dioxide. The feeding is over ... | 12/30/2008 |
| 7470630 | Approach to reduce parasitic capacitance from dummy fill An integrated circuit includes a semiconductor substrate and multiple dielectric layers stacked on the substrate. Multiple interconnect metal lines and dummy metals are embedded in the dielectric layers. At least one of the dummy metals is substantially thinner than... | 12/30/2008 |
| 7465675 | Method of forming a phase change memory device having a small area of contact Methods of fabricating a phase change memory device having a small area of contact are provided. The method includes forming a lower interlayer insulating layer on a semiconductor substrate, and forming a lower conductor pattern within the lower inter-insulating lay... | 12/16/2008 |
| 7462560 | Process of physical vapor depositing mirror layer with improved reflectivity A process of physical vapor depositing mirror layer with improved reflectivity is disclosed. A wafer is loaded into a PVD tool comprising a degas chamber, a Ti/TiN sputter deposition chamber, a cooling chamber, and an aluminum sputter deposition chamber. A wafer deg... | 12/09/2008 |
| 7459367 | Method of forming a vertical P-N junction device A P-N junction device and method of forming the same are disclosed. The P-N junction device may include a P-N diode, a PiN diode or a thyristor. The P-N junction device may have a monocrystalline or polycrystalline raised anode. In one embodiment, the P-N junction d... | 12/02/2008 |
| 7459361 | Semiconductor device with ferroelectric capacitor and fabrication method thereof A semiconductor device fabrication method includes the steps of forming a conductive plug in an insulating layer on a semiconductor substrate so as to be connected to an element on the substrate; forming a titanium aluminum nitride (TiAlN) oxygen barrier film over t... | 12/02/2008 |
| 7452770 | Reduced cell-to-cell shorting for memory arrays Bottom electrodes of memory cell capacitors are recessed to prevent electrical shorts between neighboring memory cells. A partially fabricated memory cell capacitor has a bottom electrode comprising titanium nitride (TiN) and hemispherical grained (HSG) silicon. The... | 11/18/2008 |
| 7442649 | Etch with photoresist mask A method for etching a dielectric layer over a substrate is provided. A photoresist mask is formed over the dielectric layer. The substrate is placed in a plasma processing chamber. An etchant gas comprising NF3 is provided into the plasma chamber. A plas... | 10/28/2008 |
| 7442979 | Reduced cell-to-cell shorting for memory arrays Bottom electrodes of memory cell capacitors are recessed to prevent electrical shorts between neighboring memory cells. A partially fabricated memory cell capacitor has a bottom electrode comprising titanium nitride (TiN) and hemispherical grained (HSG) silicon. The... | 10/28/2008 |
| 7427328 | Large-area nanoenabled macroelectronic substrates and uses therefor A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational c... | 09/23/2008 |
| 7425490 | Reducing reactions between polysilicon gate electrodes and high dielectric constant gate dielectrics In a metal gate replacement process, a gate electrode stack may be formed of a dielectric covered by a sacrificial metal layer covered by a polysilicon gate electrode. In subsequent processing of the source/drains, high temperature steps may be utilized. The sacrifi... | 09/16/2008 |
| 7419907 | Eliminating metal-rich silicides using an amorphous Ni alloy silicide structure The present invention provides a method for producing thin nickel (Ni) monosilicide or NiSi films (having a thickness on the order of about 30 nm or less), as contacts in CMOS devices wherein an amorphous Ni alloy silicide layer is formed during annealing which elim... | 09/02/2008 |
| 7416988 | Semiconductor device and fabrication process thereof A method of fabricating a semiconductor device includes the steps of modifying a damaged layer containing carbon and formed at a semiconductor surface by exposing the damaged layer to oxygen radicals to form a modified layer, and removing the modified layer by a wet... | 08/26/2008 |
| 7413912 | Microsensor with ferroelectric material and method for fabricating the same A microsensor fabricated with a ferroelectric material and a fabrication method therefor are provided. The microsensor includes a support, an insulating layer on the support, a first electrode on the insulating layer, a ferroelectric layer having at least a metal on... | 08/19/2008 |
| 7413913 | Semiconductor device and method of manufacturing the same Two ferroelectric capacitors including a PZT film are connected to one MOS transistor. Electrodes of the ferroelectric capacitor are arranged above a main plane of a substrate parallel to the main plane. Therefore, high capacity can be obtained easily. Furthermore, ... | 08/19/2008 |
| 7410873 | Method of manufacturing a semiconductor device A method of forming a semiconductor device uses an anneal technique to planarize and round corners of a trench formed in a substrate. The substrate is annealed under a normal pressure in an inert atmosphere, such as an atmosphere containing one of argon, helium, and... | 08/12/2008 |
