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| Number | Title | Issue Date |
| 7132305 | Method of fabricating an in-plane switching liquid crystal display device An array substrate for use in an in-plane switching liquid crystal display device has a plurality of common electrodes and a plurality of pixel electrodes. One of the common electrodes is formed at the same time with the plurality of pixel electrodes using a transpa... | 11/07/2006 |
| 6794279 | Passivating inorganic bottom anti-reflective coating (BARC) using rapid thermal anneal (RTA) with oxidizing gas A method is provided, the method including forming a gate dielectric layer above a substrate layer and forming a gate conductor layer above the gate dielectric layer. The method also includes forming an inorganic bottom anti-reflective coating layer above the gate c... | 09/21/2004 |
| 6660637 | Process for chemical mechanical polishing A chemical mechanical polishing process rotates a wafer having an alignment mark at a wafer rotation rate and a polishing surface at an off-matched rotation rate. The wafer rotation rate and the off-matched rotation rate are not equal. The wafer rotating ... | 12/09/2003 |
| 5877538 | Bidirectional trench gated power MOSFET with submerged body bus extending underneath gate trench A trench power MOSFET includes a body region which is not shorted to the source region and which is entirely covered by the source region within each cell of the MOSFET. The body region within each MOSFET cell is brought to the surface of the substrate (o... | 03/02/1999 |
| 5869893 | Semiconductor device having a trapezoidal joint chip A semiconductor device comprises at least two semiconductor elements connected together at a connecting region of the semiconductor elements. At least one joint chip is adhered to the connection region of the semiconductor elements for connecting the semi... | 02/09/1999 |
| 5866936 | Mesa-structure avalanche photodiode having a buried epitaxial junction A mesa-structure avalanche photodiode in which a buffer region in the surface of the mesa structure effectively eliminates the sharply-angled, heavily doped part of the cap layer that existed adjacent the lightly-doped n-type multiplication layer and p-ty... | 02/02/1999 |
| 5859455 | Non-volatile semiconductor memory cell with control gate and floating gate and select gate located above the channel A non-volatile semiconductor memory cell includes a semiconductor substrate with a source and a drain formed therein. A channel is defined between the source and the drain. Atop the channel is a floating gate which is controlled by the X-control line and ... | 01/12/1999 |
| 5847431 | Reduced capacitance transistor with electro-static discharge protection structure An apparatus is disclosed for providing a reduced-capacitance transistor with ESD protection that can be fabricated using standard processes. The transistor includes a substrate, a source region formed in the substrate, and a well region also formed in th... | 12/08/1998 |
| 5844318 | Aluminum film for semiconductive devices A semiconductor contact structure formed by a method that deposits an aluminum film limiting the growth of voids and notches in the aluminum film and forms an aluminum film with a reduced amount of voids and notches. The first step of the method is to for... | 12/01/1998 |
| 5844250 | Field emission element with single crystalline or preferred oriented polycrystalline emitter or insulating layer A process for manufacturing a field emission element including a substrate, and an emitter and a gate each arranged on the substrate is provided. The emitter is formed at at least a tip portion thereof with an electron discharge section, which is formed o... | 12/01/1998 |
| 5844306 | Die pad structure for solder bonding A lead frame having a die pad of such a shape that prevents scattering of solder to lead when a chip is mounted on the lead frame, and a semiconductor device using such a lead frame are provided. The lead frame includes a die pad having a region surrounde... | 12/01/1998 |
| 5834820 | Circuit for providing isolation of integrated circuit active areas The provision of an isolation gate connecting unassociated active areas of adjacent transistors formed in a semiconductor substrate provides effective isolation of the adjacent transistors with no additional process steps required. The isolation gate is t... | 11/10/1998 |
| 5834811 | Salicide process for FETs In this structure, the lightly doped layers that form the upper portions of the source and drain regions extend inwards towards the gate region, thereby satisfying the design requirements of low area and high resistivity at the interface, but not outwards... | 11/10/1998 |
| 5834805 | Dynamic random access memory circuit array and memory cell A semiconductor processing method of forming dynamic random access memory circuitry includes, a) providing an electrically conductive capacitor cell plate substrate; b) providing an electrically insulative layer over the cell plate; c) providing a layer o... | 11/10/1998 |
| 5834840 | Net-shape ceramic processing for electronic devices and packages An electronic device package is provided, consisting of reaction bonded silicon nitride structural and dielectric components and conductor, resistor, and capacitor elements positioned with the package structural components. The package consists of a ceram... | 11/10/1998 |
| 5834851 | SRAM having load transistor formed above driver transistor Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of ... | 11/10/1998 |
| 5834843 | Multi-chip semiconductor chip module A semiconductor device including a plurality of chip units each defined by a side wall and arranged in a state such that a side wall of a chip unit abuts a corresponding side wall of an adjacent chip unit, and an interconnection structure for interconnect... | 11/10/1998 |
| 5834809 | MIS transistor semiconductor device A MIS transistor comprises a semiconductor substrate having a first conductivity type, a source region and a drain region disposed in the semiconductor substrate in spaced-apart relation from one another and having a second conductivity type, and an insul... | 11/10/1998 |
| 5831281 | Thin film transistor A thin film transistor of this invention includes: a source and drain regions formed on an insulating base region; and a conductive layer connected to the source and drain regions. The conductive layer has a layered structure of an Al-containing metal fil... | 11/03/1998 |
| 5828121 | Multi-level conduction structure for VLSI circuits This invention deals with the formation of the multi-level electrode metal structure and the interconnecting inter-level metal studs used in the fabrication of VLSI circuits. After the metal layers have been formed the inter-level dielectric material used... | 10/27/1998 |
| 5828101 | Three-terminal semiconductor device and related semiconductor devices A semiconductor device has trenches formed on the surface of a semiconductor. The device passes a main current through a channel formed between the trenches and controls the main current with the use of gate electrodes buried in the trenches. The main cur... | 10/27/1998 |
| 5821562 | Semiconductor device formed within asymetrically-shaped seed crystal region Into an amorphous silicon film, catalyst elements for accelerating the crystallization are introduced. After patterning the amorphous silicon films in which the catalyst elements have been introduced into an island pattern, a heat treatment for the crysta... | 10/13/1998 |
| 5821614 | Card type semiconductor device A card type semiconductor device includes a main circuit board and a first sub-circuit-board equipped with a main memory. The main circuit board is connected to the first sub-circuit-board through an FPC. A first TCP equipped with the CPU and a second TCP... | 10/13/1998 |
| 5821560 | Thin film transistor for controlling a device such as a liquid crystal cell or electroluminescent element A thin film transistor which includes an insulation base, first and second gate electrodes, first and second insulation layers, an active layer of semiconductor material, a source electrode and a drain electrode, in which a lateral length of the first gat... | 10/13/1998 |
| 5817556 | Method of manufacturing a semiconductor memory device including memory cells having connected source regions A method of manufacturing a semiconductor memory device having a plurality of memory cells arranged in matrix includes forming a first masking layer on a semiconductor substrate of a first conductivity type and patterning the first masking layer to form a... | 10/06/1998 |
| 5814836 | Semiconductor device requiring fewer masking steps to manufacture A semiconductor device requiring fewer masking steps to manufacture. The semiconductor device includes the following layers (from bottom up): (1) a substrate; (2) a gate electrode formed on a first portion of the substrate; (3) a first semiconductor layer... | 09/29/1998 |
| 5814866 | Semiconductor device having at least one field oxide area and CMOS vertically modulated wells (VMW) with a buried implanted layer for lateral isolation having a first portion below a well, a second portion forming another, adjacent well, and a vertical po CMOS vertically modulated wells have a structure with a buried implanted layer for lateral isolation (BILLI). This structure includes a field oxide area, a first retrograde well of a first conductivity type, a second retrograde well of a second conductivi... | 09/29/1998 |
| 5814832 | Electron emitting semiconductor device An electron emitting semiconductor device is provided with a P-type semiconductor layer arranged on a semiconductor substrate having an impurity concentration. A Schottky barrier electrode is arranged on a surface of the P-type semiconductor layer. Plural... | 09/29/1998 |
| 5811847 | PSZT for integrated circuit applications An integrated circuit memory, MMIC, or other device including a dielectric comprising lead-tin zirconium-titanium oxide (PSZT). The proportion of tin ranges from 30% to 50% of the total amount of tin, zirconium and titanium. The dielectric is formed by ap... | 09/22/1998 |
| 5808340 | Short channel self aligned VMOS field effect transistor A field effect transistor with a trench or groove gate having V-shaped walls is formed in a semiconductor substrate and a gate oxide is grown on the V-shaped walls to the surface of substrate and filled with a gate electrode material, such a polysilicon. ... | 09/15/1998 |
| 5804877 | Low-resistance contact on a compound semiconductor Generally, and in one form of the invention, a method is disclosed for forming an ohmic contact on a GaAs surface 20 comprising the steps of depositing a layer of InGaAs 22 over the GaAs surface 20, and depositing a layer of TiW 24 on the layer of InGaAs ... | 09/08/1998 |
| 5804859 | Power semiconductor device having over-current protection A semiconductor device having an input terminal and an output terminal includes at least one high power device for supplying output current as an output section, and over-current limiting circuits, each including a over-current detection circuit, for limi... | 09/08/1998 |
| 5804853 | Stacked electrical device having regions of electrical isolation and electrical connections on a given stack level A semiconductor structure having electrical conductors positioned over each other, but electrically isolated from each other, is disclosed. The lower conductor has a recess in its upper surface, and the recess is at least partially filled with an oxide-ty... | 09/08/1998 |
| 5804843 | Solid state pickup device for suppressing smear signals In a solid state image pickup device including a semiconductor substrate, a photo/electro conversion element and a register formed within the semiconductor substrate, and an photoshield layer having a slit-type aperture for limiting light incident to the ... | 09/08/1998 |
| 5804871 | Lead on chip semiconductor device having bus bars and crossing leads Along the column of bonding pad (1), bidding terminal portions (2c), (3c), (4a), (5a) of bus bars (2), (3), and signal lines (4), (5) are arranged; principal wiring portions (2a), (3a) are made to extend in a 3-dimensional crossing configuration with resp... | 09/08/1998 |
| 5801432 | Electronic system using multi-layer tab tape semiconductor device having distinct signal, power and ground planes Electronic systems using separate and distinct conductive layers for power and ground are insulated from one another and a patterned signal conductive layer to form a flexible substrate for mounting a semiconductor die in a semiconductor device assembly o... | 09/01/1998 |
| 5801444 | Multilevel electronic structures containing copper layer and copper-semiconductor layers A low temperature annealed Cu silicide or germanide layer on the surface of a single crystalline semiconductor substrate of Si or Ge is used in interconnection metallization for integrated circuits. The Cu silicide or germanide layer is preferably formed ... | 09/01/1998 |
| 5801410 | Ferroelectric capacitors including extended electrodes A ferroelectric capacitor includes a substrate and a capacitor electrode on the substrate. A ferroelectric layer is provided on the first capacitor electrode, and a first insulating layer on the ferroelectric layer has a first contact hole therein exposin... | 09/01/1998 |
| 5798555 | Enhancement-depletion logic based on Ge mosfets The present invention discloses a method of forming an oxide layer on a layer of germanium including the steps of depositing a layer of aluminum arsenide on the layer of germanium, of exposing the layer of aluminum arsenide to an oxidizing gas mixture so ... | 08/25/1998 |
| 5793115 | Three dimensional processor using transferred thin film circuits A multi-layered structure is fabricated in which a microprocessor is configured in different layers and interconnected vertically through insulating layers which separate each circuit layer of the structure. Each circuit layer can be fabricated in a separ... | 08/11/1998 |
