| Patent No. | Patent Title: |
| 5595925 | Method for fabricating a multiple well structure for providing mu... |
| 5583068 | Process for forming a capacitor having a metal-oxide dielectric |
| 5552337 | Method for manfacturing a capacitor for a semiconductor memory de... |
| 5543347 | Method of forming silicon film having jagged surface |
| 5536674 | Process for forming a static-random-access memory cell |
| 5532182 | Method for fabricating stacked capacitor of a DRAM cell |
| 5527729 | Method of manufacturing a capacitor having metal electrodes |
| 5525534 | Method of producing a semiconductor device using a reticle having... |
| 5521107 | Method for forming a field-effect transistor including anodic oxi... |
| 5521116 | Sidewall formation process for a top lead fuse |
| 5516705 | Method of forming four layer overvoltage protection device |
| 5514615 | Method of producing a semiconductor memory device having thin fil... |
| 5514611 | Method of manufacturing a semiconductor memory device having a re... |
| 5510274 | Method of controlling a carrier lifetime in a semiconductor switc... |
| 5510298 | Method of interconnect in an integrated circuit |
| 5508220 | Method of forming antifuses having minimum areas |
| 5508233 | Global planarization process using patterned oxide |
| 5506175 | Method of forming compound stage MEM actuator suspended for ... |
| 5506164 | Method of manufacturing a semiconductor device having a cylindric... |
| 5504029 | Method of producing semiconductor integrated circuit device havin... |
| 5504037 | Method of forming optimized thin film metal interconnects in inte... |
| 5504028 | Method of forming a dynamic random memory device |
| 5504025 | Method of fabricating a read-only memory cell configuration havin... |
| 5501998 | Method for fabricating dynamic random access memory cells having ... |
| 5502007 | Method of forming flat surface of insulator film of semiconductor... |
| 5502008 | Method for forming metal plug and/or wiring metal layer |
| 5502000 | Method of forming a antifuse structure with increased breakdown a... |
| 5500384 | Method for manufacturing a bit line via hole in a memory cell |
| 5498579 | Method of producing semiconductor device layer layout |
| 5498563 | Method of manufacturing a static random access memory device incl... |
| 5496758 | Fabrication process of a semiconductor memory device having a mul... |
| 5496776 | Spin-on-glass planarization process with ion implantation |
| 5496751 | Method of forming an ESD and hot carrier resistant integrated cir... |
| 5494840 | Method for manufacturing DRAM memory cells having a thin metal ox... |
| 5494841 | Split-polysilicon CMOS process for multi-megabit dynamic memories... |
| 5494852 | High capacity semiconductor dopant deposition/oxidization process... |
| 5492868 | Capped reflow process to avoid contact autodoping and supress tun... |
| 5492848 | Stacked capacitor process using silicon nodules |
| 5492851 | Method for fabricating attached capacitor cells in a semiconducto... |
| 5492856 | Method of forming a semiconductor device having a LC element |
Quotables 
PatentStorm News
