Did You Know...
...that the video game, Pong, was invented by a guy who graduated at the bottom of his engineering class? Nolan Bushnell spent more time running the games at a local amusement park than he did on his studies at the University of Utah. His dreams of working for Disney's amusement empire were dashed when the company wouldn't hire him. Taking a boring job, Nolan daydreamed about electronic versions of popular games. He invented Pong, the first video game, and went on to found Atari Co.
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| Number | Title | Issue Date |
| 7197526 | Method and apparatus for calculating the remainder of a modulo division A non-iterative technique for calculating the remainder of modulo division, which requires significantly fewer operations than the traditional iterative technique for the same calculation. The number of calculations required in the present invention is independent o... | 03/27/2007 |
| 6889355 | Method and apparatus for data transmission using multiple transmit antennas A method and apparatus for increasing the data rate and providing antenna diversity using multiple transmit antennas is disclosed. A set of bits of a digital signal are used to generate a codeword. Codewords are provided according to a channel code. Delay elements m... | 05/03/2005 |
| 6810500 | Method for mapping a two-dimensional data array in a memory A memory mapping method for mapping a data array into a memory. The memory mapping method provides the two-directional access in the data array. The memory mapping method first equally divides each row of the data array into some basic units based on the number of t... | 10/26/2004 |
| 6772383 | Combined tag and data ECC for enhanced soft error recovery from cache tag errors A computer data signal comprises a first code group and a second code group. The first code group has a first symbol and an error detection code for the first symbol. The second code group has a second symbol and an error correction code. The error correction code p... | 08/03/2004 |
| 6760871 | Circuit, system and method for arranging data output by semiconductor testers to packet-based devices under test An apparatus, system, and method for testing packet-based semiconductor devices by using simplified test data packets. Simplified test data packets are generated by conventional memory testers in one format. The simplified test data packets are realigned to another,... | 07/06/2004 |
| 6742147 | Information recording medium, and method and apparatus for managing defect thereof An information recording medium includes a disk information area; a user area including a plurality of sectors; and a spare area including at least one sector which, when at least one of the plurality of sectors included in the user area is a defective sector, is us... | 05/25/2004 |
| 6738936 | Method for testing communication line to locate failure according to test point priorities in communication line management system A method for locating a failure of a communication line according to self-adjusted priorities of the test points in the order of high failure probability in a communication line management system, includes the steps of organizing the test points, information on the ... | 05/18/2004 |
| 6697979 | Method of repairing integrated circuits An arrangement and a method are provided for replacing defective units, which can be any desired unit of a chip (e.g., arithmetic and logic units), with a function unit. The arrangement and the method provide for performing self-tests more easily, less ex... | 02/24/2004 |
| 6694473 | Parallel signal decoding method The invention discloses a signal decoding method for C3 decoding on a data storage medium. The data storage medium contains a lot of sectors, and each sector contains two C3 codes. Each C3 code contains a plurality of P codes and Q codes. The syndrome ope... | 02/17/2004 |
| 6694459 | Method and apparatus for testing a data retrieval system A method for testing data retrieval systems that uses codes embedded within the test data set to confirm that retrieved data is legal, valid, is the right type of data, belongs to the right owner, and is accurate. The embedded codes and translation keys a... | 02/17/2004 |
| 6694480 | Receiving apparatus, receiving method, transmission system and transmission method Multiplex transmission apparatus 10 on the transmitting side multiplexes received signals from non-voice signal input output apparatus 14 and voice signal input output apparatus 16, and also transmits the multiplexed signal from communications network 30 ... | 02/17/2004 |
| 6691267 | Technique to test an integrated circuit using fewer pins A technique to implement functions requiring fewer pins of an integrated circuit to serially transfer data into the integrated circuit for multiple logic blocks. By reducing the required pins, this permits downbonding of the integrated circuit into a pack... | 02/10/2004 |
| 6687866 | LSI having a built-in self-test circuit A LSI includes a logic circuit, a PLL circuit and a built-in self-test (BIST) circuit. When the PLL circuit detects a phase lock of the system clock signal of the LSI with a reference clock signal under the condition of presence of a test instruction sign... | 02/03/2004 |
| 6684362 | Method and apparatus for connecting manufacturing test interface to a global serial bus including an I2 c bus Methods and apparatus are provided for connecting a manufacturing test interface to a global serial bus, such as an inter integrated circuit (I2 C) bus. Input/output buffer logic buffers data to be transferred to and from the global serial bus.... | 01/27/2004 |
| 6681364 | Cyclic redundancy check for partitioned frames An improved method and system for generating a frame check sequence. A multiple-bit data string, M, is received in which M is of the form: M is thereafter parsed into multiple subframes of the form: and The subframes are padded with zeros resulting in subframes of ... | 01/20/2004 |
| 6675341 | Extended error correction for SEC-DED codes with package error detection ability An apparatus and method is provided for correcting data words resulting from a package fail within a memory array in which coded data is divided into a plurality of multi-bit packages of b bits each. The coded data comprises n-bit words with r error corre... | 01/06/2004 |
| 6671839 | Scan test method for providing real time identification of failing test patterns and test bist controller for use therewith A method of scan testing an integrated circuit to provide real time identification of a block of test patterns having at least one failing test pattern comprises performing a number of test operations and storing a test response signature corresponding to... | 12/30/2003 |
| 6671843 | Method for providing user definable algorithms in memory BIST A method performed by a software design tool for providing an algorithm to a BIST controller that tests memory within a circuit. The method includes reading a description of a user defined test algorithm for a BIST controller, translating the description ... | 12/30/2003 |
| 6671846 | Method of automatically generating schematic and waveform diagrams for isolating faults from multiple failing paths in a circuit using input signal predictors and transition times Relevant logic cells and waveforms of a circuit are automatically identified, traced and displayed by using conventional simulation, schematic viewing and waveform viewing tools. The input and output waveforms to and from each logic cell and a transition ... | 12/30/2003 |
| 6671836 | Method and apparatus for testing memory A method and apparatus for testing DRAM is described. The method and apparatus causes the DRAM pins to be reconfigured to provide a direct path between the memory core and the DRAM pins. This reconfiguration allows the memory core to be "seen" without pro... | 12/30/2003 |
| 6668342 | Apparatus for a radiation hardened clock splitter A clock splitter circuit provides a radiation hardened pair of adjustably non-overlapping complementary clocks. The circuit includes a pair of clock inverter legs. Each clock inverter leg can include an and-or-inverter (AOI) circuit having a first input c... | 12/23/2003 |
| 6662327 | Method for clustered test pattern generation A method for clustered pattern generation maintains high fault coverage of a circuit under test while it reduces the amount of test data to store by using clusters of correlated test patterns. A test pattern generator stores only a small number of center ... | 12/09/2003 |
| 6662330 | Joint range reject automatic repeat request protocol ARQ protocol useful for transferring delay-sensitive data blocks between sending and receiving devices (102, 104) over an error-prone communication link (116). The ARQ protocol allows either the sender or receiver to initiate termination of the transfer f... | 12/09/2003 |
| 6662328 | Method of making logic devices A method of testing a logic device that includes the steps of identifying a first test vector corresponding to a test failure resulting from testing of the logic device (10), converting the first test vector from an input pin format into state data associ... | 12/09/2003 |
| 6658612 | Test signal generating circuit of a semiconductor device with pins receiving signals of multiple voltage levels and method for invoking test modes A signal generating circuit of a semiconductor device comprises n input test pins for receiving respective coded input signals. At least one of the input signals is coded in more than two possible levels, such as 3 levels or four levels. The device also i... | 12/02/2003 |
| 6658608 | Apparatus and method for testing ferroelectric memories A ferroelectric integrated circuit memory device includes: a plurality of memory cells, each including a ferroelectric material, a plurality of conducting lines, each connected to or connectable to a selected one of the memory cells; a drive circuit for a... | 12/02/2003 |
| 6654919 | Automated system for inserting and reading of probe points in silicon embedded testbenches A method for inserting and reading probe points in a silicon embedded testbench comprising the steps of (a) reading a simulation list of probe points, (b) enabling access to the list of probe points, (c) generating a core, and (d) displaying or comparing ... | 11/25/2003 |
| 6654920 | LBIST controller circuits, systems, and methods with automated maximum scan channel length An integrated circuit (10) comprising combinational circuitry (13). The integrated circuit further comprises a plurality of scan channels (SC1 through SC4). Each of the plurality of scan channels comprises a number of scan elements (EC11 throug... | 11/25/2003 |
| 6651203 | On chip programmable data pattern generator for semiconductor memories A semiconductor memory chip in accordance with the present invention includes a first memory array to be tested including a plurality of memory cells arranged in rows and columns, the memory cells being accessed to read and write data thereto by employing... | 11/18/2003 |
| 6651206 | Method of design for testability, test sequence generation method and semiconductor integrated circuit Flip-flops (FFs) to replace with scan FFs are selected for an integrated circuit designed at the gate level in order that the integrated circuit has an n-fold line-up structure. All FFs in an integrated circuit are temporarily selected as FFs to replace w... | 11/18/2003 |
| 6647518 | Methods and apparatus for estimating a bit error rate for a communication system There is provided programmability, automatic error correction, flexible inter-path implementation for a bit error rate estimator. The bit error rate estimator uses an initialization configuration for a number of memory elements of a reference pattern gene... | 11/11/2003 |
| 6647521 | Memory testing method and apparatus, and computer-readable recording medium A memory testing method tests a memory by writing test data to and reading test data from the memory. Data is successively read from the memory is synchronism with a clock and the data is compared. The memory testing method then judges a defect in the mem... | 11/11/2003 |
| 6647524 | Built-in-self-test circuit for RAMBUS direct RDRAM A built-in-self-test (BIST) circuit for RAMBUS DRAM is disclosed. Unlike other conventional memory devices, a RAMBUS DRAM operates at a much higher speed (e.g., 400 MHz) with a complicated protocol imposed on its input stimuli. In order to provide at-spee... | 11/11/2003 |
| 6643813 | Method and apparatus for reliable and efficient data communications The reliability of data communication by is improved analyzing plural data units in a group or a block rather than analyzing individual data units. For example, at the time that a transmitter desires or needs to send a polling request to a receiver, there... | 11/04/2003 |
| 6643812 | Manipulation of hardware control status registers via boundary scan A method and system for injecting scanned data into rings located in different system devices comprises configuring a utility buffer from a specified scan path by combining one or more fields from a database having one or more fields, locking a specified ... | 11/04/2003 |
| 6643804 | Stability test for silicon on insulator SRAM memory cells utilizing bitline precharge stress operations to stress memory cells under test An apparatus, program product, and method of testing a silicon-on-insulator (SOI) static random access memory (SRAM) introduce switching history effects to a memory cell during testing to stress the memory cell such that a reliable determination of stabil... | 11/04/2003 |
| 6640323 | Testing system for evaluating integrated circuits, a testing system, and a method for testing an integrated circuit A burn-in testing system for evaluating a circuit under test, the system including a burn-in board having a plurality of receptacles, at least one of which being sized to receive the circuit under test, test interface circuitry supported by the board and ... | 10/28/2003 |
| 6636993 | System and method for automatic deskew across a high speed, parallel interconnection A method and system performs automatic deskew tuning and alignment across high-speed, parallel interconnections in a high performance digital system to compensate for inter-bit skew. Rather than using a VDL, digital elements such as registers and multiple... | 10/21/2003 |
| 6637002 | Decoder for error correcting block codes A decoder for decoding block error correction codes is described. The decoder includes a first search circuit to find roots of an error location polynomial corresponding to an error location and a second search circuit to find roots of an error location p... | 10/21/2003 |
| 6634007 | Algebraic soft decoding of reed-solomon codes An algorithmic soft-decision decoding method for Reed-Solomon codes proceeds as follows. Given the reliability matrix .PI. showing the probability that a code symbol of a particular value was transmitted at each position, computing a multiplicity matrix M... | 10/14/2003 |
