| Patent No. | Patent Title: |
| 7197526 | Method and apparatus for calculating the remainder of a modulo di... |
| 6889355 | Method and apparatus for data transmission using multiple transmi... |
| 6810500 | Method for mapping a two-dimensional data array in a memory |
| 6772383 | Combined tag and data ECC for enhanced soft error recovery from c... |
| 6760871 | Circuit, system and method for arranging data output by semicondu... |
| 6742147 | Information recording medium, and method and apparatus for managi... |
| 6738936 | Method for testing communication line to locate failure according... |
| 6697979 | Method of repairing integrated circuits |
| 6694473 | Parallel signal decoding method |
| 6694459 | Method and apparatus for testing a data retrieval system |
| 6694480 | Receiving apparatus, receiving method, transmission system and tr... |
| 6691267 | Technique to test an integrated circuit using fewer pins |
| 6687866 | LSI having a built-in self-test circuit |
| 6684362 | Method and apparatus for connecting manufacturing test interface ... |
| 6681364 | Cyclic redundancy check for partitioned frames |
| 6675341 | Extended error correction for SEC-DED codes with package error de... |
| 6671839 | Scan test method for providing real time identification of failin... |
| 6671843 | Method for providing user definable algorithms in memory BIST |
| 6671846 | Method of automatically generating schematic and waveform diagram... |
| 6671836 | Method and apparatus for testing memory |
| 6668342 | Apparatus for a radiation hardened clock splitter |
| 6662327 | Method for clustered test pattern generation |
| 6662330 | Joint range reject automatic repeat request protocol |
| 6662328 | Method of making logic devices |
| 6658612 | Test signal generating circuit of a semiconductor device with pin... |
| 6658608 | Apparatus and method for testing ferroelectric memories |
| 6654919 | Automated system for inserting and reading of probe points in sil... |
| 6654920 | LBIST controller circuits, systems, and methods with automated ma... |
| 6651203 | On chip programmable data pattern generator for semiconductor mem... |
| 6651206 | Method of design for testability, test sequence generation method... |
| 6647518 | Methods and apparatus for estimating a bit error rate for a commu... |
| 6647521 | Memory testing method and apparatus, and computer-readable record... |
| 6647524 | Built-in-self-test circuit for RAMBUS direct RDRAM |
| 6643813 | Method and apparatus for reliable and efficient data communicatio... |
| 6643812 | Manipulation of hardware control status registers via boundary sc... |
| 6643804 | Stability test for silicon on insulator SRAM memory cells utilizi... |
| 6640323 | Testing system for evaluating integrated circuits, a testing syst... |
| 6636993 | System and method for automatic deskew across a high speed, paral... |
| 6637002 | Decoder for error correcting block codes |
| 6634007 | Algebraic soft decoding of reed-solomon codes |
Bizarre Patents 
PatentStorm News
