Bizarre Patents
Decorative Jeweled Wheel Cover
An improved wheel is provided wherein decorative items such as gem stones are embedded in either the wheel surface, a special mounting section attached to the wheel surface, or to a spoke strap that wraps around each spoke and positions embedded gem stones on the outside surface of the spoke.
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| Number | Title | Issue Date |
| 7426593 | Information processing system, reproducing terminal device and reproducing method, information processing device and method, and program for synchronous display of content In a transmitting terminal, a first displaying section displays, synchronously with a receiving terminal, a portion of content that has been transmitted to the receiving terminal. A second displaying section displays a portion of the content that has yet to be trans... | 09/16/2008 |
| 7418527 | Method and device for identifying devices connected to a communication network The invention concerns a device in a communication network, the device comprising a component for obtaining a permanent identifier of the devices connected to the network and a component for establishing an association table between the permanent identifier of a dev... | 08/26/2008 |
| 7386647 | System and method for processing an interrupt in a processor supporting multithread execution A system and method is disclosed for the handling of interrupts by the disabled logical processors of an information handling system or computer system. An interrupt service routine is written to the read-only portion of system memory. Upon receipt of an interrupt, ... | 06/10/2008 |
| 7386645 | System on a chip with an arbitration unit to grant right of access to a common resource in response to conflicting requests for access from initiator modules, and storage key incorporating the arbitration unit An electronic system comprises a defined number N of functional modules, including a defined number P of initiator modules and a defined number Q of target modules, where N, P and Q are integer numbers such that 2≦P≦N and 1≦Q≦N. In the event of a plurality o... | 06/10/2008 |
| 7380037 | Data transmitter between external device and working memory A data transmitter includes a bus master circuit. The bus master circuit obtains the right to use a CPU bus and directly performs data transmission to and from a working memory connected to the CPU bus through a CPU interface section and the CPU bus. ... | 05/27/2008 |
| 7373443 | Multiple interfaces in a storage enclosure Provided is a method for interfacing with storage units, including a backplane, at least one slot in the storage enclosure for receiving one storage unit, and two physical interfaces on the backplane for at least one slot. The storage unit is capable of being positi... | 05/13/2008 |
| 7373447 | Multi-port processor architecture with bidirectional interfaces between busses A multi-port processor architecture having a first bus, a second bus and a central processing unit. The central processing unit having a first and second ports coupled to first and second busses respectively. A first bus to second bus bi-directional interface couple... | 05/13/2008 |
| 7373442 | Method for using an expander to connect to different storage interconnect architectures Provided is a system for interfacing with storage units, including a backplane, at least one slot in the storage enclosure for receiving one storage unit, and two physical interfaces on the backplane for at least one slot. The storage unit is capable of being positi... | 05/13/2008 |
| 7370134 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 05/06/2008 |
| 7370130 | Core logic device of computer system A core logic device of a computer system includes a programmable interrupt controller (PIC), an input/output advanced programmable interrupt controller (I/O APIC) and a virtual wire unit. The PIC outputs a control signal to the virtual wire unit via an interrupt pin... | 05/06/2008 |
| 7356630 | Processor control device for stopping processor operation A processor control device includes a processor executing an instruction, a module coupled to the processor through a bus and processing independently from the processor, the module is provided in a plural number and a polling processing unit coupled to each module,... | 04/08/2008 |
| 7356638 | Using out-of-band signaling to provide communication between storage controllers in a computer storage system A system provides communication between components of a computer data storage system using out-of-band (OOB) signaling. The system includes a plurality of data storage devices having a local controller for directing data flow to each of the plurality of data storage... | 04/08/2008 |
| 7353316 | System and method for re-routing signals between memory system components A plurality of memory modules used in a computer system each include a memory hub that is connected to a plurality of memory devices. The memory modules are connected to each other in series so that signals are coupled between the memory modules and the memory hub c... | 04/01/2008 |
| 7353307 | Linking addressable shadow port and protocol for serial bus networks Linking addressable shadow port (LASP) and protocol allows addressing the LASP and configuring the connection of multiple Secondary Test Access Ports (TAPs) of the LASP using a single protocol or protocol bypass inputs. Multiple LASPs are cascaded and the connection... | 04/01/2008 |
| 7350013 | Bus communication apparatus for programmable logic devices and associated methods A programmable logic device (PLD) includes programmable logic circuitry and a bridge circuitry. The bridge circuitry includes a first interface circuitry and a first signal select circuitry. The first signal select circuitry couples to the first interface circuitry ... | 03/25/2008 |
| 7350010 | Method and an apparatus for switching root cells for a computer system without requiring the computer system to be re-booted Embodiments of the present invention pertain to methods and systems are described for switching root cells for a computer system without requiring the computer system to be re-booted. In one embodiment, objects are used to represent fixed registers associated with a... | 03/25/2008 |
| 7343439 | Removable modules with external I/O flexibility via an integral second-level removable slot The functionality provided to electronic devices by application specific removable modules is enhanced by viewing the removable modules as first-level removable modules and providing them with at least one second-level removable slot for selectively nesting second-l... | 03/11/2008 |
| 7337261 | Memory apparatus connectable to a host system having a USB connector An integrated semiconductor memory device for use within an integrated USB memory apparatus has a controller, a flash memory in communication with the controller, a USB interface circuit in communication with the memory controller, and an integrated circuit package ... | 02/26/2008 |
| 7337249 | I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can ... | 02/26/2008 |
| 7337258 | Dynamically allocating devices to buses Devices are assigned to different buses at development time as well as dynamically during operation, based on actual performance. At development time, bus assignment can be determined based on experiments and direct observation of how devices behave in various confi... | 02/26/2008 |
| 7334071 | Expansion of cross-domain addressing for PCI-express packets passing through non-transparent bridge A PCI-Express compatible switch is provided with two or more, internal virtual buses. In one embodiment, at least one of the plural virtual buses is designated as a special bus that is limited to having no more than 16 devices on it even though the protocol allows f... | 02/19/2008 |
| 7330920 | Signal initiator and method for on-demand communication A method is provided for on-demand communications in a communication network with support for a plurality of communication units participating in a common communication, which includes multiple signal initiators, each supplying a signal, which are virtually simultan... | 02/12/2008 |
| 7320046 | Optical disc drive having a control board and driving unit in separate locations An optical disc drive that includes a driving unit including a spindle motor to rotate an optical disc, an optical pickup to access the optical disc, and a connection board connected to a computer. A control board to control the driving unit, is installed at an inte... | 01/15/2008 |
| 7310696 | Method and system for coordinating interoperability between devices of varying capabilities in a network Systems and methods for coordinating the interoperability of devices with varying capabilities are disclosed. A host device may inquire as to the capabilities of a storage device in a storage network. A routing device may receive this response, and if the routing de... | 12/18/2007 |
| 7308521 | Multi-port communications integrated circuit and method for facilitating communication between a central processing chipset and multiple communication ports A system includes a core chipset that is configured to communicate with a central processing unit. The system includes a memory bridge configured to communicate with memory. An accelerated graphics processor configured to communicate with a graphics device. An input... | 12/11/2007 |
| 7302511 | Chipset support for managing hardware interrupts in a virtual machine system In one embodiment, an apparatus includes a set of multiplex blocks coupled with an interrupt controller and multiple interrupt request lines, and a virtual machine monitor block (VMM) coupled to the set of multiplex blocks. Each multiplex block corresponds to a dist... | 11/27/2007 |
| 7296103 | Method and system for dynamically selecting wafer lots for metrology processing The present invention is generally directed to various methods and systems for dynamically controlling metrology work in progress. In one illustrative embodiment, the method comprises providing a metrology control unit that is adapted to control metrology work flow ... | 11/13/2007 |
| 7293127 | Method and device for transmitting data using a PCI express port A data port operates to support symmetric PCI Express-type data transfers when in a first mode of operation. When in a second mode of operation, at least a portion of the data port connections are used to support an asymmetric PCI Express-type data transfer. The asy... | 11/06/2007 |
| 7290076 | Optmizing an interrupt-latency or a polling rate for a hardware platform and network profile combination by adjusting current timer values for both receive and transmit directions of traffic and calculating a new timer value to be used for both receive and transmit directions of traffic Provided are techniques for determining a timer value. An advised number of packets per interrupt for both receive and transmit directions of traffic is determined. Current timer values for both receive and transmit directions of traffic are adjusted based on the de... | 10/30/2007 |
| 7290075 | Performing arbitration in a data processing apparatus An apparatus for arbitration within a data processing apparatus between a plurality of transfers to be routed over a corresponding plurality of paths provided by an interconnect circuit. The plurality of paths include a shared connection, the data processing apparat... | 10/30/2007 |
| 7287114 | Simulating multiple virtual channels in switched fabric networks Methods and systems, including computer program products, implementing techniques for receiving, at a first device of a switched fabric network, requests from one or more applications, each request being destined for a second device of the network, the first device ... | 10/23/2007 |
| 7281072 | Redundant external storage virtualization computer system A redundant external storage virtualization computer system. The redundant storage virtualization computer system includes a host entity for issuing an IO request, a redundant external storage virtualization controller pair coupled to the host entity for performing ... | 10/09/2007 |
| 7272680 | Method of transferring data between computer peripherals An improved method for accessing data is disclosed, which is capable of increasing the efficiency of data access by reducing the time consumed by registering data in the system memory while transferring data between computer peripherals. ... | 09/18/2007 |
| 7272678 | DSP bus monitoring apparatus and method A bus monitor is provided as a tool for developing, debugging and testing a system having an embedded processor. The bus monitor resides within the same chip or module as the processor, which allows connection to internal processor buses not accessible from external... | 09/18/2007 |
| 7272681 | System having parallel data processors which generate redundant effector date to detect errors A high assurance processing system includes a plurality of data processors coupled in parallel, a bridge coupled to the plurality of data processors, and an input/output processor coupled to the bridge for coupling to a sensor and an effector. Sensor data passes to ... | 09/18/2007 |
| 7269682 | Segmented interconnect for connecting multiple agents in a system In various embodiments, an apparatus comprises a plurality of agents and an interconnect. In one embodiment, the plurality of agents includes first through fourth agents. The interconnect comprises a plurality of segments that are switchable (e.g. using a plurality ... | 09/11/2007 |
| 7266629 | Data transfer control device and electronic instrument generating interface signal of signal type according to interface information set in internal register A data transfer control device including: a link controller which analyzes a received packet transferred from a host-side data transfer control device through a serial bus; an interface circuit which generates interface signals and outputs the generated interface si... | 09/04/2007 |
| 7263573 | Wireless USB hardware scheduling In a wireless USB data transfers over UWB, software configures hardware thresholds to control data transfer in a manner that uses bandwidth for good connections over bad connections, given the high error rate experienced with wireless USB. Periodic transfers are fir... | 08/28/2007 |
| 7263565 | Bus system and integrated circuit having an address monitor unit A bus system for handling changes in an access address range of a subject-of-access or a bus master is disclosed. The bus system can have an address monitor unit including a table which is shared among a plurality of bus masters and stores therein access right infor... | 08/28/2007 |
| 7263569 | Method and system for distributing power in a computer system An apparatus for distributing power in a computer system includes a power supply device; a processing device including a CPU module and a plurality of I/O modules; and an insert line coupled between the power supply and the processing device. The insert line is conn... | 08/28/2007 |
