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| Number | Title | Issue Date |
| 5317749 | Method and apparatus for controlling access by a plurality of processors to a shared resource A latch manager enabling multiple processors in a multiprocessor system to gain access to a shared resource. Resource access is controlled by the use of a latch-control word. There is one latch-control word associated with each of the shared resources in ... | 05/31/1994 |
| 5313592 | Method and system for supporting multiple adapters in a personal computer data processing system The present invention provides a method and system for providing communication between a number of applications and a number of devices disposed in various relative locations in a data processing system through an interface that is capable of accessing on... | 05/17/1994 |
| 5278970 | Method for efficient utilization of removable data recording media A method for efficiently utilizing data recording media in a data processing system performing data compression beneath the level of the host processor is disclosed. To improve the ability of a recording media to be copied without increasing host processo... | 01/11/1994 |
| 5276815 | Input and output processing system for a virtual computer A virtual computer system has a plurality of virtual computers and a virtual computer monitor for monitoring the virtual computers and for providing translation information describing the relationship between a virtual identification of the input/output a... | 01/04/1994 |
| 5276887 | Bus arbitration system for granting bus access to devices following two-wire bus arbitration protocol and devices following three-wire bus arbitration protocol A bus arbitration system is capable of granting access to an expansion bus to devices following two-wire bus arbitration protocol or a three-wire bus arbitration protocol. The bus arbitration system receives a plurality of bus request signals from a plura... | 01/04/1994 |
| 5276808 | Data storage buffer system and method A system and method for striping data to multiple storage devices is provided. One embodiment of the present invention sequentially gates data to a plurality of buffers, wherein only those buffers corresponding to storage devices in use are induced to gat... | 01/04/1994 |
| 5274771 | System for configuring an input/output board in a computer An automatically configurable I/O board and associated software avoids any need for jumpers, switches, or other configuration changes upon installation of the board. Utilization of the main computer capability to select addresses and values likely to be a... | 12/28/1993 |
| 5265258 | Partial-sized priority encoder circuit having look-ahead capability In an integrated circuit microprocessor, an M-bit priority encoder circuit indicates the highest priority bit position that is set in a first portion of an N-bit (N generally being greater than M) data word and provides control information regarding the n... | 11/23/1993 |
| 5263137 | Syntax converting apparatus for decomposing different portions of a data string differently depending on whether a data string is an external type data string A syntax converting apparatus performs conversions between an abstract syntax and a transfer syntax in a presentation layer, defined by an Open Systems Interconnection (OSI). The presentation layer determines the syntax, which describes application proces... | 11/16/1993 |
| 5255372 | Apparatus for efficiently interconnecing channels of a multiprocessor system multiplexed via channel adapters Apparatus for efficiently interconnecting OEMI channels of a multiprocessor facility. A plurality of channel adapters are connected to individual channels from a plurality of processors. A supervisory interrupt driven microprocessor receives a link reques... | 10/19/1993 |
| 5255373 | Decreasing average time to access a computer bus by eliminating arbitration delay when the bus is idle A method and apparatus to improve computer bus access time. A bus is described which has sequential control states and fixed transaction times. Without the invention, arbitration may be delayed as the bus sequences through control states. With the inventi... | 10/19/1993 |
| 5253357 | System for determining pluggable memory characteristics employing a status register to provide information in response to a preset field of an address A system is described that includes an arithmetic logic unit that senses the presence of a circuit module in a connector, wherein one type of circuit module, if present, automatically provides a set of signals on a predetermined pin set that indicates cha... | 10/12/1993 |
| 5253345 | Point of sale register system A register system for facilitating point of sale transactions of any of a plurality of products, each of the products having a bar code encoded product identification associated therewith, is disclosed. The register system comprises a central computer for... | 10/12/1993 |
| 5253348 | Method of arbitration for buses operating at different speeds In a bus adapter coupling a system bus and an I/O bus which operate at different speeds and contain a plurality of devices, a method by which an arbiter in the bus adapter prevents contention for ownership of both buses by a device on either of the buses.... | 10/12/1993 |
| 5253344 | Method and apparatus for dynamically changing the configuration of a logically partitioned data processing system A request is made by a system in a first logical partition, within a logically partitioned data processing system, to dynamically change the I/O configuration of the host system in a way that affects a system in a second logical partition. The hypervisor ... | 10/12/1993 |
| 5251305 | Apparatus and method for preventing bus contention among a plurality of data sources An apparatus for preventing bus contention among a plurality of data sources is described which creates signals to be used to disable two of three data sources which share a common bus immediately prior to a bus access cycle. The circuit employs a negativ... | 10/05/1993 |
| 5249297 | Methods and apparatus for carrying out transactions in a computer system A protocol for carrying out transactions in a multiple-processor computer system comprises: dividing the transaction cycle into four quadrature states, an arbitrate state, an I/O state, a slave address state and a virtual memory state. The protocol enable... | 09/28/1993 |
| 5247632 | Virtual memory management arrangement for addressing multi-dimensional arrays in a digital data processing system A virtual memory management arrangement translates a process virtual address of an item of data in an array of data into a physical address for use in accessing a memory. A virtual address translation portion forms, in response to a process virtual addres... | 09/21/1993 |
| 5247622 | ID processing dedicated SCSI bus interface logic circuit An ID processing dedicated SCSI bus interface logic circuit comprising a self ID decoder for decoding a self ID input; a priority encoder for encoding the highest priority ID on a SBI data bus; an ID Win comparator for comparing the self ID input with an ... | 09/21/1993 |
| 5247685 | Interrupt handling in an asymmetric multiprocessor computer system Two independently operating microprocessors share common control, data and address buses. A first of the microprocessors is assigned, when it is on the buses, to respond to all maskable interrupts by causing placement of an interrupt vector on the bus at ... | 09/21/1993 |
| 5241630 | Device controller with a separate command path between a host and the device and a separate data path including a first in, first out memory between the host and the device A SCSI bus controller which has a separate data path from the SCSI bus to the host bus and a separate command path for use to communicate with a local microprocessor. The local microprocessor is connected to a dual port RAM, the other port of which is con... | 08/31/1993 |
| 5239648 | Computer network capable of accessing file remotely between computer systems Each computer system of the computer network according to the present invention has a management information storage portion for storing information with respect to an access authority in accordance with an owner ID and a conversion rule storage portion f... | 08/24/1993 |
| 5237695 | Bus contention resolution method for network devices on a computer network having network segments connected by an interconnection medium over an extended distance A method is used to perform arbitration between network devices connected to one of a first network segment and a second network segment, where the first network segment is connected to the second network segment by a long interconnection medium over an e... | 08/17/1993 |
| 5237694 | Processing system and method including lock buffer for controlling exclusive critical problem accesses by each processor There is described a system and method for use in a processing system of the type including a plurality of processor subsystems, each processor subsystem including a processor, and being coupled together and to a shared memory by a common bus, wherein the... | 08/17/1993 |
| 5235695 | Apparatus for efficient utilization of removable data recording media An apparatus for efficiently utilizing data recording media performs data compression beneath the level of the host processor is disclosed. To improve the ability of a recording media to be copied without increasing host processor overhead, the control un... | 08/10/1993 |
| 5233692 | Enhanced interface permitting multiple-byte parallel transfers of control information and data on a small computer system interface (SCSI) communication bus and a mass storage system incorporating the enhanced interface An improved interface system based in part on the SCSI standard is provided. A single cable data bus simultaneously transfers several bytes of information between two devices. The interface system transfers multiple-byte commands, messages, status informa... | 08/03/1993 |
| 5230056 | Battery powered information terminal apparatus wherein the clock frequency is switched dependent upon the battery voltage An information terminal apparatus has a capability of continuously operating, when a battery capacity drop is detected, and maintaining the battery capacity at a certain level for an extended period. When the battery capacity drops to cause a battery volt... | 07/20/1993 |
| 5228129 | Synchronous communication interface for reducing the effect of data processor latency Incoming data which is required to be passed to a desired storage location under the control of a processor is received by a store prior to being passed to a serial communications controller. The store is preferably a FIFO store and stores the data at an ... | 07/13/1993 |
| 5226121 | Method of bit rate de-adaption using the ECMA 102 protocol A method of bit rate de-adaption between an adapted data rate and a user data rate using the ECMA 102 protocol. The user data is transmitted from a data adapter to a user terminal at a first data rate, the adapted data is received by the data adapter at a... | 07/06/1993 |
| 5226124 | Communication interface between a radio control transmitter and a computer data bus An interface circuit for use between a radio control transmitter equipped with joysticks and a standard data bus of a personal type computer. The interface circuitry includes a microcontroller operated as a reformatter for signals received from the remote... | 07/06/1993 |
| 5226173 | Integrated data processor having mode control register for controlling operation mode of serial communication unit A reception unit for providing data supplied from a serial input circuit to an inner bus and a transmission unit for providing the data supplied from the inner bus to a serial output circuit hold at least two types of control procedures selected from HDLC... | 07/06/1993 |
| 5226129 | Program counter and indirect address calculation system which concurrently performs updating of a program counter and generation of an effective address A processor capable of processing a variable word length instruction has a program counter controlled to indicate the head of an instruction by the value of the program counter. There are provided an adder for summing the length of decoded portions in the... | 07/06/1993 |
| 5222231 | Data processing system having a resume function and an operating method thereof A data processing method and apparatus have a resume function and use a password. When a power switch of a data processing system is turned on while it is selected that the resume function is to be enabled and the password is to be collated, the data proc... | 06/22/1993 |
| 5222227 | Direct memory access controller for a multi-microcomputer system A multi-microcomputer system comprising a first microcomputer system, a second microcomputer system, and a direct memory access controller which has a function of controlling a data transfer operation that is executed between the first microcomputer syste... | 06/22/1993 |
| 5218703 | Circuit configuration and method for priority selection of interrupts for a microprocessor A circuit configuration and a method for priority selection of interrupts for a microprocessor in an integrated circuit which includes a central processing unit, a central interrupt node connected to the central processing unit, N interrupt sources for pr... | 06/08/1993 |
| 5218692 | Digital pulse timing parameter measuring device A pulse input device has a standard time generator for outputting standard time information by counting a system clock signal; an input circuit for sampling input signal information from a plurality of channels in synchronization with the standard time in... | 06/08/1993 |
| 5210871 | Interprocessor communication for a fault-tolerant, mixed redundancy distributed information processing system A method for resolving access contentions by a plurality of processing sites having the same or different redundancies to a shared communications system wherein the start of the access contention process is first synchronized for all contending sites. A d... | 05/11/1993 |
| 5206936 | Apparatus for exchanging channel adapter status among multiple channel adapters A device information interface for a channel to channel I/O device having a plurality of channel adapters. A device interface bus interconnects each of the channel adapters, permitting an exchange of data between channel adapters. A virtual device storage... | 04/27/1993 |
| 5202998 | Fast, simultaneous multi-processor system status communication interface Each processor in a multi-processor system has an associated interface circuit which comprises a register for storing a flag bit status and evaluation logic for comparing the stored flag bit status with an update status from the associated processor. The ... | 04/13/1993 |
| 5202963 | Method and apparatus for adapting a remote communications controller to a variety of types of communications modems A data processing system includes at least one modem connected from a communications link to the remote devices and at least one modem controller. A modem adaptor stores scripts for directing modem control related operation, each script being a sequence o... | 04/13/1993 |
