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| Number | Title | Issue Date |
| RE40660 | Configurable glueless microprocessor interface A host control interface for use in interfacing an external host processor with internal control/status registers of an integrated circuit is provided. In accordance with the teachings of the present invention, the control interface selectively couples the integrate... | 03/10/2009 |
| RE40635 | 32 bit generic asynchronous bus interface using read/write strobe byte enables A display controller having an asynchronous bus interface is provided. In one embodiment a display controller configured to communicate with a microprocessor is provided. The display controller operates at a first clock speed and microprocessor operates at a second ... | 02/10/2009 |
| 7464212 | Method and apparatus for determining compatibility between devices Embodiments are generally directed to a method and apparatus for determining compatibility between devices. In one embodiment, a table including a module's parameters and rules associated therewith is obtained from a module. The rules are applied to a slot's paramet... | 12/09/2008 |
| 7464206 | Semiconductor device and method of connecting the same According to the present invention, there is provided a semiconductor device comprising: a power line to be externally supplied with a power supply voltage; a ground line for grounding; a first sig... | 12/09/2008 |
| 7464213 | Memory adapter and unit including independent radio circuit and removable memory store Data stored in a memory unit can be transmitted to an external apparatus such as a PC, a television or a printer without relying on operations carried out on a host apparatus, onto which the memory unit has been mounted. The memory unit includes a memory card and an... | 12/09/2008 |
| 7464215 | Cradle device, control method and computer program for controlling the attitude of an imaging device At least one exemplary embodiment is directed to a cradle device which inhibits driving of a pan/tile driving unit in the event of an imaging device being detached from the cradle device, and also receiving a control command of the imaging device from a camera. The ... | 12/09/2008 |
| 7461193 | Network media access controller embedded in a programmable logic device—receive-side client interface A receive-side client interface for a media access controller embedded in an integrated circuit having programmable logic is described. A media access controller core includes a receive engine. A receive-side datapath is coupled to the media access controller core. ... | 12/02/2008 |
| 7461195 | Method and system for dynamically adjusting data transfer rates in PCI-express devices Method and system for configuring a PCI-Express device is provided. The method includes determining if a number of lanes supported by the PCI-Express device is equal to or greater than a number X, after a receiver is detected by the PCI-Express device; and setting a... | 12/02/2008 |
| 7461192 | Interface for bridging out-of-band information and preventing false presence detection of terminating devices A device includes a first interface to receive a signal from a first communication link, wherein the receive signal includes out-of-band (OOB) information. A detector coupled to the first interface detects the OOB information. An encoder coupled to the detector enco... | 12/02/2008 |
| 7457906 | Method and apparatus for shared I/O in a load/store fabric An apparatus and method is provided for allowing I/O devices to be shared and/or partitioned among a plurality of processing complexes within the load/store fabric of each of the processing complexes without requiring modification to the operating system or driver s... | 11/25/2008 |
| 7454552 | Switch with transparent and non-transparent ports There are disclosed apparatus and methods for switching. Transparent and non-transparent ports are provided. Data units are transferred between the transparent ports, between the transparent and non-transparent ports, and between the non-transparent ports. ... | 11/18/2008 |
| 7451250 | Methods and apparatus for providing automatic high speed data connection in portable device In a portable FireWire compatible device, a direct memory access (DMA) bus switch coupled by way of a DMA bus to a central processing unit (CPU), a local hard drive (HDD), and a FireWire port, provides a direct connection between the FireWire port and the HDD bypass... | 11/11/2008 |
| 7447827 | Multi-port bridge device A bridge device electrically connected to a first AGP bus, a second AGP bus, and a PCI bus is provided. The bridge device has a first bridge, a second bridge, and a controller. The first bridge is electrically connected between the first AGP bus and the second AGP b... | 11/04/2008 |
| 7447824 | Dynamic lane management system and method A dynamic lane management system comprises at least one downstream device of a computer system configured to dynamically initiate a lane width re-negotiation operation with at least one upstream device of the computer system in response to a detection of at least on... | 11/04/2008 |
| 7447822 | Hot-plug control system and method A hot-plug control system and method is applied to a computer device, wherein the computer device is provided with a PCI-E (Peripheral Component Interconnect Express) bus, at least one PCI-E slot having a power switch and an indicator light, a power control unit and... | 11/04/2008 |
| 7447819 | Information processing apparatus and SMI processing method thereof An information processing apparatus includes: a CPU; a controller including a signal transmission unit configured to supply an SMI (system management interrupt) signal to the CPU; a multifunctional device having a plurality of functions each potentially causing an S... | 11/04/2008 |
| 7447821 | U3 adapter A U3 adapter with a first interface to operationally couple the U3 adapter with a host system; and a second interface for interfacing with a memory device is provided. An application is executed by the U3 adapter and the application uses information stored on the me... | 11/04/2008 |
| 7444456 | SRAM bus architecture and interconnect to an FPGA An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of the FPGA through an element which includes a pass transistor connect... | 10/28/2008 |
| 7444452 | Computer system with a PCI express interface A computer system comprises a chip set having a PCI Express controller with a preset lane width, a PCI Express connector with a relative bigger lane width, and a PCI Express interfaced apparatus with the bigger lane width. In the system, only part of the contacts wi... | 10/28/2008 |
| 7444450 | Method and system for detecting excessive interrupt processing for a processor A method and system is provided for detecting excessive interrupt processing for a processor. The method includes the operation of defining an interrupt processing period during which measuring of interrupts for a processor takes place. The amounts of time being spe... | 10/28/2008 |
| 7441064 | Flexible width data protocol A microprocessor interface system including a system bus with a bus clock and a data signal group in which multiple devices are coupled to the system bus. Each device is configured to perform a half-width data transaction on the system bus in which a doubleword is t... | 10/21/2008 |
| 7441061 | Method and apparatus for inter-module communications of an optical network element Inter-module communications of an optical network element are described herein. In one embodiment, an exemplary optical network element includes multiple functional modules arranged in multiple shelves and multiple management modules for coordinating the functional ... | 10/21/2008 |
| 7437496 | Hot swap adapter There is disclosed a hot swap adapter having a circuit board, a power connector, a data connector and a circuit board connector. The circuit board may include one more logic devices. The power connector, the data connector and the circuit board connector may attach ... | 10/14/2008 |
| 7433989 | Arbitration method of a bus bridge A bus bridge interfaces a primary-side bus with a plurality of secondary-side buses. The primary side bus is a local bus in a system and the secondary-side buses are external buses connected to the system. The bus bridge supports a plurality of kinds of operations o... | 10/07/2008 |
| 7430627 | Adaptive reader-writer lock A method and computer system for dynamically selecting an optimal synchronization mechanism for a data structure in a multiprocessor environment. The method determines a quantity of read-side and write-side acquisitions, and evaluates the data to determine an optima... | 09/30/2008 |
| 7426601 | Segmented interconnect for connecting multiple agents in a system In various embodiments, an apparatus comprises a plurality of agents and an interconnect. In one embodiment, the plurality of agents includes first through fourth agents. The interconnect comprises a plurality of segments that are switchable (e.g. using a plurality ... | 09/16/2008 |
| 7426592 | Management function setting method for intelligent platform management interface A management function setting method for dynamically setting a plurality of management functions of an intelligent platform management interface (IPMI) of a computer system, allows a system manager to obtain a system status through the IPMI, and set customized comma... | 09/16/2008 |
| 7426602 | Switch for bus optimization There is disclosed a bus optimization technique. Pursuant to the bus optimization technique, the output buffer and output logic are removed from port units of a switch and are included with a control matrix in the switch. Data units received in a first port unit of ... | 09/16/2008 |
| 7421528 | Network media access controller embedded in a programmable logic device—address filter A method for address filtering is described. A host interface including device registers is provided. A user program is initiated for loading of data and control information respectively into a first data register and a control register of the device registers. Resp... | 09/02/2008 |
| 7421532 | Switching with transparent and non-transparent ports There are disclosed apparatus and methods for switching. Transparent and non-transparent ports are provided. Data units are transferred between the transparent ports, between the transparent and non-transparent ports, and between the non-transparent ports. ... | 09/02/2008 |
| 7415554 | System and method for parallel data transmission A system for parallel data transmission including a master device and a slave device is provided. The master device includes a first and a second I/O ports for outputting a read signal and a write signal, respectively. The slave device includes a third and a fourth ... | 08/19/2008 |
| 7415558 | Communication steering for use in a multi-master shared resource system New approaches for providing communication between multiple masters (12, 14) and one or more shared resources (24, 30, 100) are needed. One example of a resource that may need to be shared is circuitry complying with the Universal Serial Bus (USB) stan... | 08/19/2008 |
| 7412551 | Methods and apparatus for supporting programmable burst management schemes on pipelined buses Methods and apparatus for supporting programmable burst management schemes on pipelined buses. The apparatus includes a plurality of bus masters (masters), configured in a plurality of clusters, and a plurality of target sub-groups. Each target sub-group includes on... | 08/12/2008 |
| 7409476 | System and method for USB controllers A USB controller is provided with multiple logic channels that share same physical address and data bus at an interface between the host system and the USB Host Controller; and dataports used by the host system to read and/or write data to the USB Host Controller. A... | 08/05/2008 |
| 7406557 | Programmable logic device including programmable interface core and central processing unit A programmable logic device (PLD) includes a central processing unit (CPU) and a programmable interface coupled to the CPU, wherein the programmable interface includes a core designated by a user. The programmable interface core allows devices, both on and off-chip,... | 07/29/2008 |
| 7404025 | Software programmable dynamically reconfigurable scheme for controlling request grant and masking for ultra high priority accessor during arbitration A method for arbitration grants access to an ultra high priority device if the ultra high priority device requests access. This access is limited to a selectable number of accesses. Thereafter the ultra high priority device is masked from requesting access for a sel... | 07/22/2008 |
| 7404026 | Multi media card with high storage capacity A multi media card includes a plurality of memory modules and an extraneous command decoder. The extraneous command decoder decodes a predetermined command for determining a selected memory module to be accessed from the plurality of memory modules, when a predeterm... | 07/22/2008 |
| 7401171 | Methods and structure for SAS expander initiating communication to a SAS initiator to identify changes in the SAS domain Methods and structures within a SAS expander for initiating communication with one or more SAS initiators in a SAS domain to inform the initiators of sensed changes in the domain without the need for a full SAS Discovery process. In one aspect hereof, the expander m... | 07/15/2008 |
| 7398346 | Bus system for use with information processing apparatus A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection control... | 07/08/2008 |
| 7395365 | Data transfer control system, electronic instrument, program, and data transfer control method A data transfer control system includes: a port control section which controls ports P1 and P2 respectively connected with an electronic instrument PC1 and an electronic instrument PC2; and a bus reset issue section which issues a bus res... | 07/01/2008 |
