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"Transmission of documents via telephone wires is possible in principle, but the apparatus required is so expensive that it will never become a practical proposition."
Dennis Gabor, British physicist
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| Number | Title | Issue Date |
| 5740467 | Apparatus and method for controlling interrupts to a host during data transfer between the host and an adapter An apparatus and method for transferring data in a data processing system to and from a host system. A communication adapter or input/output controller device is provided in which queues are utilized to transfer information between the adapter or controll... | 04/14/1998 |
| 5649124 | High-speed bus system for simultaneous serial and parallel data transfer and a method of operating the system A high-speed bus system which combines at least one parallel bus and at least one serial bus for simultaneous parallel and serial data transfer with serial data transfer taking place after connection setup at the same time as normal transfer of data and/o... | 07/15/1997 |
| 5642489 | Bridge between two buses of a computer system with a direct memory access controller with accessible registers to support power management A bridge for interfacing buses in a computer system having an industry standard architecture (ISA) bus and a peripheral controller interconnect (PCI) bus is coupled between the ISA and PCI buses. The bridge has a direct memory access (DMA) control circuit... | 06/24/1997 |
| 5619661 | Dynamic arbitration system and method A dynamic arbitration system for controlling the data transfer between primary and secondary buses in a personal computer has master and target components on both buses. Primary and secondary bus arbiters are included in a bridge circuit, and initially op... | 04/08/1997 |
| 5603036 | Power management system for components used in battery powered applications A control circuit for a computer component circuit which includes oscillator apparatus for providing square wave pulses at a prescribed frequency, gating apparatus for providing the square wave pulses at an output terminal for use as a clock for the compo... | 02/11/1997 |
| 5592674 | Automatic verification of external interrupts A method for the automatic verification of external interrupts in modern processor architectures under a very wide range of instruction sequences provides almost complete expected results from each of the involved interrupts. In particular, the method all... | 01/07/1997 |
| 5564027 | Low latency cadence selectable interface for data transfers between busses of differing frequencies A bus interface with resources to selectively optimize burst mode data transfers from one bus to another through an automated selection and generation of a cadence. In one form, the cadence is selected based upon memory access latency characteristics, the... | 10/08/1996 |
| 5559964 | Cable connector keying A cable connector having pins reserved for conveying data through shorting can be used to automatically convey pertinent information concerning the cable, the system to which the cable is connected, whether the cable is attached at all, or any combination... | 09/24/1996 |
| 5557756 | Chained arbitration A bus arbitration circuit, having a state machine which receives a processor request signal, a request signal from each of a group of internal input/output devices, and an external device request signal. The state machine sends a processor grant signal, a... | 09/17/1996 |
| 5557757 | High performance integrated processor architecture including a sub-bus control unit for generating signals to control a secondary, non-multiplexed external bus An integrated processor that employs a bus interface unit to accommodate high performance data transfers via an external peripheral interconnect bus with multiplexed address/data lines. The peripheral interconnect bus, which may be a PCI standard bus, acc... | 09/17/1996 |
| 5555413 | Computer system and method with integrated level and edge interrupt requests at the same interrupt priority A computer system that has a processor that services interrupts in response to receipt of a signal at the interrupt request has a first device and a second device coupled to the processor. The first device is capable of transmitting a first interrupt requ... | 09/10/1996 |
| 5555383 | Peripheral component interconnect bus system having latency and shadow timers A PCI system is provided with a shadow register and a shadow timer. When a master device sends an address designating a target device that is connected to another bus, the device's latency value is recorded in the shadow register. While the PCI-PCI bridge... | 09/10/1996 |
| 5553250 | Bus terminating circuit A bus terminating circuit is provided on each of a plurality of SCSI devices connected to each other through an SCSI bus line. A first terminating resistor is inserted between each of the signal lines and a power source line of the bus line and a second t... | 09/03/1996 |
| 5553249 | Dual bus adaptable data path interface system A single chip data path gate array interface links a central processing unit, operating at a first clock rate and single word protocol, to dual system busses operating at a second clock rate and multiple-word protocol. The data path interface holds comman... | 09/03/1996 |
| 5553295 | Method and apparatus for regulating the output voltage of negative charge pumps A regulation circuit which includes circuitry for furnishing a reference voltage, a voltage divider for furnishing a voltage provided by a charge pump circuit, a comparator for comparing the output of the charge pump circuit with the reference voltage, an... | 09/03/1996 |
| 5550988 | Apparatus and method for performing error correction in a multi-processor system In a multi-processor system having a first processor, a second processor, and a bus coupling the first processor to the second processor, a method for correcting an erroneous signal corresponding to the first processor while maintaining lock atomicity. Wh... | 08/27/1996 |
| 5550990 | Physical partitioning of logically continuous bus Arrangements for physically partitioning a bus having a well defined architecture as a physical entity, wherein the partitioning is logically transparent to a computer and devices which communicate through the bus and serves to avoid problems potentially ... | 08/27/1996 |
| 5546550 | Method for assuring equal access to all input/output devices coupled to a SCSI bus The present invention is useful in a data processing system having a data processor coupled to a SCSI channel disposed for transmitting and receiving data between the data processor and a peripheral storage subsystem having a multiplicity of disk drives. ... | 08/13/1996 |
| 5544289 | Method and apparatus for controlling and communicating with business office devices A method and apparatus for controlling and communicating with business office devices, such as copiers, facsimiles and/or printers. The present invention communicates and controls various modules of business devices which allow an external device such as ... | 08/06/1996 |
| 5542110 | DMA controller which releases buses to external devices without relinquishing the bus utility right A DMA controller having an acceptance circuit, a transfer control circuit and a release ordering circuit. The acceptance circuit receives a temporary bus release request and its withdrawal from an external device, once the DMA controller acquires a bus ut... | 07/30/1996 |
| 5539910 | Circuit configuration for monitoring the supply voltage of a processor unit A circuit configuration for monitoring a supply voltage of a processor unit being clocked by an oscillator and requiring a minimum supply voltage, includes an undervoltage detector being connected to the processor unit. The undervoltage detector is in ope... | 07/23/1996 |
| 5537554 | Method and apparatus for controlling and communicating with business office devices A method and apparatus for controlling and communicating with business office devices, such as copiers, facsimiles and/or printers. The present invention communicates and controls various modules of business devices which allow an external device such as ... | 07/16/1996 |
| 5526494 | Bus controller A bus controller reduces the bus access wait time, to improve the performance of a processing unit that frequently accesses a main storage. The bus controller comprises a request signal generation unit for generating a bus right request signal according t... | 06/11/1996 |
| 5511205 | System for distributed power management in portable computers A system and method for managing power in a portable, pen-based notebook computer. The system and method provides for minimizing power consumption by collecting and interpreting power related data of various processing elements while hiding many of the de... | 04/23/1996 |
| 5483642 | Bus system for use with information processing apparatus A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connect... | 01/09/1996 |
| 5471674 | Computer system with plug-in override of system ROM A portable computer system with a special connector, on the motherboard, into which a field-installable boot card can be inserted. The special motherboard connector is wired so that the operator, by setting connections on the field-installable boot card, ... | 11/28/1995 |
| 5471621 | Information processing systems having a main CPU and a sub-CPU which controls the overall system to achieve power savings An information processing system in which a sub-CPU is provided besides a main CPU to carry out those kinds of processing and power supply control that may be executed at time intervals of a short period, so that the power consumption of the information p... | 11/28/1995 |
| 5471626 | Variable stage entry/exit instruction pipeline An instruction pipeline includes a sequence of interconnected pipeline stages, each stage dedicated to one of several operations executed on data in a digital processing device. Control words govern execution of the operations as they progress through the... | 11/28/1995 |
| 5459840 | Input/output bus architecture with parallel arbitration A high performance bus suitable for high speed internetworking applications which is based on three bus phase types, including an arbitration phase, an address phase, and a data phase. The arbitration, address, and data phases share a single set of lines.... | 10/17/1995 |
| 5459870 | Interface circuit for controlling data transfers In a computer system including a host which operates in a pre-read mode to start a block data transfer after reading status of a peripheral device (HDD) in response to an interrupt from the peripheral device or in a post-read mode to read the status after... | 10/17/1995 |
| 5457790 | Low power consumption semiconductor integrated circuit device and microprocessor In semiconductor integrated circuit device and microprocessor including at least one functional circuit block, the start of operation of the functional circuit block is detected prior to the start of operation, the functional circuit block for which the s... | 10/10/1995 |
| 5457801 | Power saving system In a personal computer having a logic circuit constituted by low-power consumption elements such as CMOS elements, a power saving system includes a register in which control data can be set from a keyboard or by software, and switches for allowing and sto... | 10/10/1995 |
| 5454083 | Target selection response circuit for a small computer system interface A selection response circuit according to SCSI (small computer system interface), where a selection response device is designed with a digital logic having a simple structure. The present circuit comprises a bus checking unit for checking the status of an... | 09/26/1995 |
| 5454113 | Circuit configuration for protecting the operation of a computer-controlled apparatus A control unit is controlled by a computer having a reset input. A circuit configuration protects the operation of the control unit by placing a signal at the reset input for restarting the computer in the event of a malfunction. The circuit configuration... | 09/26/1995 |
| 5450591 | Channel selection arbitration A system for arbitration between competeting channels in, for example, a direct memory access (DMA) controller is described. The system arbitrates much more fairly than in the traditional `round robin` approach, especially when channel requests are not in... | 09/12/1995 |
| 5450592 | Shared resource control using a deferred operations list A method for handling attempts by multiple processing threads to access a shared system resource is disclosed. When a thread attempts to access a locked resource, the thread creates a description of the operation it intended to perform and stores the desc... | 09/12/1995 |
| 5450594 | Enhanced collision detection for ethernet network Enhanced collision detection in an Ethernet network, particularly useful for passive nodes using receive mode collision detection. When a transmitting node detects a collision, for example, using transmit mode collision detection, it activates a current s... | 09/12/1995 |
| 5446905 | Data processing apparatus having improved power supply system A data processing apparatus includes a data processing part, a power supply connector, and an original power supply device connected to the power supply connector and selected from among a commercial power source adapter outputting a direct-current voltag... | 08/29/1995 |
| 5442755 | Multi-processor system with lock address register in each processor for storing lock address sent to bus by another processor A multi-processor system wherein a plurality of processors connected to a common bus share a main storage by means of a storage controller connected to the common bus. If a processor executes a lock setting, the other processors receive the lock address s... | 08/15/1995 |
| 5440697 | Method and apparatus for simulating I/O devices A computer system comprises a CPU, a main memory, and plurality of I/O Processors (IOPs), coupled to each other by a system I/O bus. The IOPs perform slave processing functions relating to I/O devices. A simulation protocol is defined for the IOPs, whereb... | 08/08/1995 |
