| Patent No. | Patent Title: |
| 5134580 | Computer with capability to automatically initialize in a first ... |
| 5134561 | Computer system with logic for writing instruction identifying da... |
| 5093782 | Real time event driven database management system |
| 5062041 | Processor/coprocessor interface apparatus including microinstruct... |
| 5056059 | Medical monitoring system interface |
| 5056011 | Direct memory access controller with expedited error control |
| 5056060 | Printed circuit card with self-configuring memory system for ... |
| 5050061 | Apparatus for generating predetermined control data corresponding... |
| 5041968 | Reduced instruction set computer (RISC) type microprocessor execu... |
| 5041963 | Local area network with an active star topology comprising ring ... |
| 5040142 | Method of editing and circulating an electronic draft document am... |
| 5038279 | Direct hot-keying with reset of printer parameters for a secondar... |
| 5036484 | Personal computer/host emulation system for handling host data wi... |
| 5023780 | Method of operating a packet switching network |
| 5019968 | Three-dimensional vector processor |
| 5018097 | Modularly structured digital communications system for interconne... |
| 5018096 | Security administrator for automatically updating security levels... |
| 5018063 | Method for reducing cross-interrogate delays in a multiprocessor ... |
| 5012404 | Integrated circuit remote terminal stores interface for communica... |
| 5007016 | Fractal-type periodic temporal signal generator |
| 5003463 | Interface controller with first and second buffer storage area fo... |
| 4991086 | Microprogram controlled microprocessor having a plurality of inte... |
| 4987529 | Shared memory bus system for arbitrating access control among con... |
| 4980852 | Non-locking queueing mechanism for enabling a receiver device to ... |
| 4905184 | Address control system for segmented buffer memory |
| 4901233 | Computer system with logic for writing instruction identifying da... |