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Microwave Oven With Removable Storage Cassette in Dashboard of Motor Vehicle
A microwave oven adapted for use within a motor vehicle dashboard area. The microwave oven has a removable storage cassette, and slidable platforms for securing and serving containers of beverages and foods.
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| Number | Title | Issue Date |
| 8190810 | Non-volatile memory apparatus and method for accessing a non-volatile memory apparatus A non-volatile memory apparatus and a method for accessing the non-volatile memory apparatus are provided. The non-volatile memory apparatus comprises a management unit, a look-up table and a controller. The management unit comprises a plurality of data blocks and a... | 05/29/2012 |
| 8156306 | Systems and methods for using thin provisioning to reclaim space identified by data reduction processes The invention provides a system to reclaim space identified as no longer in use and comprises a vLUN, a thinly provisioned mapped LUN, a mapping layer, and a data reduction engine. Chunks of data are stored at logical chunk addresses (LCAs) in the vLUN and are mappe... | 04/10/2012 |
| 8156314 | Incremental state updates A system and method are described that manage incremental state updates in such a way that multiple threads within a processor can each operate, in effect, on their own set of state data. The system and method are applicable to any processor in which multiple thread... | 04/10/2012 |
| 8145873 | Data management method for network storage system and the network storage system built thereof A data management method for network storage system that said network storage system includes a storage network, a cluster of storage servers that provide data storage services for application servers connecting to the storage network and storage space corresponding... | 03/27/2012 |
| 8140821 | Efficient read/write algorithms and associated mapping for block-level data reduction processes A system configured to optimize access to stored chunks of data is provided. The system comprises a vLUN layer, a mapped LUN layer, and a mapping layer disposed between the vLUN and the mapped LUN. The vLUN provides a plurality of logical chunk addresses (LCAs) and ... | 03/20/2012 |
| 8112603 | Methods, systems, and computer program products for file relocation on a data storage device A method, system, and computer program product for file relocation on a data storage device are provided. The method includes initiating file relocation in response to invoking a cleaner function for a data storage device. The method also includes examining metadata... | 02/07/2012 |
| 8099638 | Apparatus and methods for tuning a memory interface The disclosure relates to a programmable virtual memory client, that includes programmable control logic configured to generate at least one data pattern sequence from a number of stored data patterns. Additionally, the virtual memory client includes virtual memory ... | 01/17/2012 |
| 8099575 | Virtual machine control program and virtual machine system The program attains compatibility of suppression of an overhead accompanying page exception handling in the case of operating a program whose amount of memory use is large on a virtual machine and suppression of the overhead accompanying page exception handling in t... | 01/17/2012 |
| 8099561 | Shared memory system for a tightly-coupled multiprocessor A shared memory system for a multicore computer system utilizing an interconnection network that furnishes tens of processing cores or more with the ability to refer concurrently to random addresses in a shared memory space with efficiency comparable to the typical ... | 01/17/2012 |
| 8099544 | Information processing apparatus and nonvolatile semiconductor memory drive According to one embodiment, a control module of a nonvolatile semiconductor memory drive has a first erase mode in which an address management table, which is indicative of a correspondency between logical block addresses and physical addresses of a nonvolatile sem... | 01/17/2012 |
| 8095853 | Digital memory with fine grain write operation Methods, systems, and apparatus for operating digital memory including determining, by a controller, a bit to be written to the digital memory and writing, by the controller, the bit. The bit may be part of a data word comprising a plurality of bits and both the det... | 01/10/2012 |
| 8095728 | Method and system for power aware I/O scheduling A method for retrieving a logical block, including receiving a request to read the logical block, and obtaining metadata associated with the logical block, wherein the metadata includes a replication type used to store the logical block and physical block locations ... | 01/10/2012 |
| 8082417 | Method for reducing pin counts and microprocessor using the same The present invention relates to a microprocessor with reduced pin counts. The microprocessor transmits a higher bit address, a lower bit address and data via a common port so that a pin for transmitting the higher bit address is omitted. In an embodiment of the pre... | 12/20/2011 |
| 8065450 | Frame transfer method and device In a frame transfer method and device by which an address space of a shared buffer can be effectively utilized without a reduction of the space even if an abnormal operation occurs in a management of the shared buffer, after frame data is written in the shared buffe... | 11/22/2011 |
| 8060776 | Mirror split brain avoidance A data storage system has two computers. Each computer is assigned to a set of data. Two copies of each set of data are maintained. A first copy is stored on a first set of disks and a second copy is stored on a second set of disks. Each time that a data is written ... | 11/15/2011 |
| 8055866 | Mirrored storage system and methods for operating a mirrored storage system A mirrored storage system for applications is provided, which enables and supports the variation and dynamic adaptation of the Recovery Point Objectives (RPO) based on policies. Furthermore, methods are provided for running such a mirrored storage system. Said mirro... | 11/08/2011 |
| 8051266 | Automatic memory management (AMM) The present invention manages the execution of multiple AMM cycles to reduce or eliminate any overlap. Specifically, the present invention provides an external supervisory process to monitor the AMM behavior of VMs on one or more nodes, and intervene when coincident... | 11/01/2011 |
| 8041924 | Location-independent raid group virtual block management A computer storage system is described. A range of volume block numbers (VBNs) is assigned to a volume. A range of storage device block numbers (DBNs) is assigned to each of a plurality of storage devices. A first mapping parameters are created to map a first range ... | 10/18/2011 |
| 8041774 | Early issue of transaction ID Early issue of transaction ID is disclosed. An apparatus comprising decoder to generate a first node ID indicative of the destination of a cache transaction from a caching agent, a transaction ID allocation logic coupled to and operating in parallel to the decoder t... | 10/18/2011 |
| 8037253 | Method and apparatus for global ordering to insure latency independent coherence A method and apparatus is described for insuring coherency between memories in a multi-agent system where the agents are interconnected by one or more fabrics. A global arbiter is used to segment coherency into three phases: request; snoop; and response, and to appl... | 10/11/2011 |
| 8037273 | Storage system logical storage area allocating method and computer system A method for allocating optimum pages to a logical volume according to the usage of the logical volume and an access characteristic is provided. A storage system is connected to a host computer, includes plural disk drives and a controller to control the plural disk... | 10/11/2011 |
| 8032689 | Techniques for data storage device virtualization A data storage device comprises virtual storage devices that are each assigned to a subset of data sectors in a non-volatile memory of the data storage device. The data storage device receives configuration metadata for configuring each of the virtual storage device... | 10/04/2011 |
| 8032712 | Storage system for staging data in random access area There is provided a storage system accessed by a host computer, comprising: an interface coupled to the host computer; a processor coupled the interface; a memory coupled to the processor; and a storage device for storing the data. The storage device comprises a fir... | 10/04/2011 |
| 8028235 | Multi-windows color adjustment system and method The invention provides a multi-windows color adjustment system and method that divides the picture frame of a display screen into three or more windows so that the user can compare the color tones of the windows and then select the preferred window. The multi-window... | 09/27/2011 |
| 8024546 | Opportunistic page largification Page tables in the last level of a hierarchical page table system are scanned for candidate page tables. Candidate page tables are converted to large pages, having a page table entry in a level before the last level of the hierarchical page table system adjusted to ... | 09/20/2011 |
| 8015366 | Accessing memory and processor caches of nodes in multi-node configurations A method for communicating between nodes of a plurality of nodes is disclosed. Each node includes a plurality of processors and an interconnect chipset. The method issues a request for data from a processor in a first node and passes the request for data to other no... | 09/06/2011 |
| 7992214 | Method for protecting memory proprietary commands A method for protecting memory proprietary command is provided. By using the logic block area (LBA) address in the header of the LBA mode, the device end can determine whether the data sector in the LBA mode includes a proprietary command. Also, by using the pre-def... | 08/02/2011 |
| 7644202 | Disk array device and method for controlling disk array device A disk array device includes at least one channel control section for receiving data input/output requests from an information processing device, at least one disk control section for sending data input/output requests to hard disk drives based on the data input/out... | 01/05/2010 |
| 7631148 | Adaptive file readahead based on multiple factors A storage system is provided that implements a file system configured to optimize the amount of readahead data retrieved for each read stream managed by the file system. The file system relies on various factors to adaptively select an optimized readahead size for e... | 12/08/2009 |
| 7603436 | Data capture and fusion from a population of device users A method and system is provided for capturing data from a population of device users with network access. A requestor may request a data capture. The requested data may include, for example, a geographical location or a desired subject matter. Devices capable of pro... | 10/13/2009 |
| 7464218 | Method for improving data throughput for a data storage device A method for improving throughput performance of a data storage device by executing an execution critical write-back data priority routine programmed into a controller of the data storage device. The method includes, determining a write-back data aging threshold lim... | 12/09/2008 |
| 7461224 | Remote copy system In asynchronous remote copy, there is time difference between data update and remote copy in a primary storage system. The primary storage system loses data unreflected on a secondary storage system in disaster and cannot control the amount of data lost. The primary... | 12/02/2008 |
| 7461200 | Method and apparatus for overlaying flat and tree based data sets onto content addressable memory (CAM) device A content addressable memory device (100) and method can have CAM blocks (102-0 to 102-29) organized in block sections (104-0 to 104-6). In an overlay mode of operation, an overlay engine (106) ca... | 12/02/2008 |
| 7457931 | Method and apparatus for estimating the effect of processor cache memory bus delays on multithreaded processor throughput An estimate of the throughput of a multi-threaded processor based on measured miss rates of a cache memory associated with the processor is adjusted to account for cache miss processing delays due to memory bus access contention. In particular, the throughput calcul... | 11/25/2008 |
| 7457927 | Memory dump of a computer system A memory dump of a memory of a computer system having a first set of bytes and a second set of bytes. The first set of bytes includes application data, and the second set of bytes includes a description of a structure of the application data. The memory dump is read... | 11/25/2008 |
| 7457921 | Write barrier for data storage integrity A system that facilitates the storage of data using a write barrier. The system interfaces to a hardware component that stores data, and includes a write barrier component that dynamically employs instructions compatible with the hardware component to ensure data in... | 11/25/2008 |
| 7454582 | Initial copy system A storage apparatus installed in a first site generates a snapshot of a copy source logical device in an intermediate logical device. Next, an external storage apparatus including a logical device corresponding to the intermediate logical device is disconnected from... | 11/18/2008 |
| 7451274 | Memory control device, move-in buffer control method A central processor executes at least a load command, a store command, and a prefetch command based on an out-of-order processing for processing commands by changing the order of executing the commands. A valid move-in buffer (MIB) detector detects the number of pri... | 11/11/2008 |
| 7447856 | Copy engine and a method for data movement A copy engine (104) is provided as an interface between firmware (108) and memory space (106) for carrying out copy operations. The copy engine has a first register (202, 203) to point to a first address and a second register (204, 205... | 11/04/2008 |
| 7447871 | Data access program instruction encoding A data processing apparatus 2 is provided which is responsive to data access instructions to perform data access operations. These data access instructions have a first form utilizing a 12-bit offset field but with a fixed addressing mode and a second form ut... | 11/04/2008 |
