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| Number | Title | Issue Date |
| 6526488 | Computer systems There is disclosed a method and apparatus for controlling access to and corruption of information in a computer system. In known "PC Virus" protection methods the boot partition becomes "Read Only" when the system is in Supervised Mode. However, Microsoft... | 02/25/2003 |
| 6523086 | Method for improving performance of read cache of magnetic disk drive A method for improving the performance of a read cache of a magnetic disk drive includes: a data transmission process for reading corresponding data from the disk in response to a data read command of a host computer, temporarily storing the corresponding... | 02/18/2003 |
| 6430653 | Disk control unit and method for prefetching according to partition information and concatenation information A disk control unit and method thereof enable read-in speed to be improved regarding a file which is stored in a fixed drive discontinuously. A prefetch decision circuit receives instructions from an instruction decode circuit. The prefetch decision circu... | 08/06/2002 |
| 6430660 | Unified memory hard disk drive system A disk controller system includes a microprocessor, a hard disk controller, a disk channel path, a host communications path, and an interface coupled to each of the microprocessor, hard disk controller, disk channel path and host communications path. A un... | 08/06/2002 |
| 6418525 | Method and apparatus for reducing latency in set-associative caches using set prediction A method and apparatus for storing and utilizing set prediction information regarding which set of a set-associative memory will be accessed for enhancing performance of the set-associative memory and reducing power consumption. The set prediction informa... | 07/09/2002 |
| 6412041 | Real time processing method of a flash memory A real time processing method of a flash memory is disclosed, which includes the steps of (1) determining whether an access to the flash memory is possible when an access to a block of the flash memory is requested in order to perform a read/write operati... | 06/25/2002 |
| 6408370 | Storage system assuring data integrity and a synchronous remote data duplexing A primary controller operates to transmit write data and a write time to a secondary controller in the earlier sequence of the write times after reporting a completion of a request for write to a processing unit. The secondary controller stores the write ... | 06/18/2002 |
| 6405294 | Data center migration method and system using data mirroring A method and system for migrating computer applications and volumes of data from a source DASD connected to a source computer system to a target DASD connected to a target computer system. The method comprises ensuring data integrity on the source DASD, i... | 06/11/2002 |
| 6401186 | Continuous burst memory which anticipates a next requested start address A system is described which uses a burst access memory and a memory controller to anticipate the memory address to be used in future data read operations as requested by a microprocessor. Either the memory controller or the memory device initiates a burst... | 06/04/2002 |
| 6397299 | Reduced latency memory configuration method using non-cacheable memory physically distinct from main memory The present invention relates to a method in a computer system, for configuring a memory subsystem, comprising selecting a subset of main memory, integrating the subset of main memory within the computer system such that the subset is physically distinct ... | 05/28/2002 |
| 6397313 | Redundant dual bank architecture for a simultaneous operation flash memory The present invention discloses sector-based redundancy that is capable of making repairs using a plurality of redundant columns of memory cells in a dual bank memory device during simultaneous operation. The simultaneous operation memory device includes ... | 05/28/2002 |
| 6397318 | Address generator for a circular buffer This invention describes an apparatus and method for the fast and efficient generation of addresses for a circular buffer involving only addition. The invention uses as input the present address, the base address, the length of the circular buffer and the... | 05/28/2002 |
| 6389521 | Data transfer control of a video memory having a multi-divisional random access memory and a multi-divisional serial access memory An image memory has a random access memory array capable of being randomly accessed; a serial access memory array partitioned into n power of 2 (n>1) divisional areas cyclically and serially accessed in asynchronism with the random access memory; data tra... | 05/14/2002 |
| 6385672 | System to optimize packet buffer utilization via selectively partitioned transmit and receive buffer portions The present invention provides a device which facilitates communications between a computer system and a data network by buffering data in transit between the computer system and the data network in a single buffer memory which can be flexibly partitioned... | 05/07/2002 |
| 6385699 | Managing an object store based on object replacement penalties and reference probabilities A computerized method, system and computer program product for managing an object store is disclosed. An exemplary method includes the the steps of: collecting performance statistics about storage repositories from which an object(s) can be retrieved; ret... | 05/07/2002 |
| 6385640 | Switching apparatus applied to a plurality of information processing systems which are closed systems An switching apparatus including an information sending unit and an information receiving unit. The information sending unit has a selecting block for selecting an information item to be sent to another information system from among information items proc... | 05/07/2002 |
| 6381682 | Method and apparatus for dynamically sharing memory in a multiprocessor system Multiple instances of operating systems execute cooperatively in a single multiprocessor computer wherein all processors and resources are electrically connected together. The single physical machine with multiple physical processors and resources is subd... | 04/30/2002 |
| 6378054 | Data backup device and method for use with a computer, and computer-readable recording medium having data backup program recorded thereon A technique related to a data backup for a computer. There are provided a selection section, an archive file creation section, and a backup processing section. The selection section selects data files satisfying given conditions from among data files stor... | 04/23/2002 |
| 6374342 | Translation lookaside buffer match detection using carry of lower side bit string of address addition There is disclosed DTLB in a microprocessor of the present invention, comprising an adder for adding a base address and a sign-extended offset address; a comparator for judging whether or not upper side 20 bits [31:12] of the base address match the base a... | 04/16/2002 |
| 6370620 | Web object caching and apparatus for performing the same A plurality of web objects are cached. A first object is within an assigned web partition. A second object is outside of the assigned web partition. The first object is placed in a first amount of space within the cache. A copy of the second object is pla... | 04/09/2002 |
| 6356990 | Set-associative cache memory having a built-in set prediction array A set-associative cache memory having a built-in set prediction array is disclosed. The cache memory can be accessed via an effective address having a tag field, a line index field, and a byte field. The cache memory includes a directory, a memory array, ... | 03/12/2002 |
| 6356974 | Architecture for state machine for controlling internal operations of flash memory An architecture for a state machine used to control the data processing operations performed on the memory cells contained in a memory array. The architecture is designed to control the performance of the operations and sub-operations used to erase and pr... | 03/12/2002 |
| 6349376 | Method for decoding addresses using comparison with range previously decoded A method for providing the results of an address decode operation involves comparing the address of an address to be decoded with the address range containing an address previously decoded in a previous address decode operation, selecting the results of t... | 02/19/2002 |
| 6339811 | Rotationally optimized seek initiation Methods and control systems for delaying a seek once a command is received to further load a buffer with read look ahead data are described. The methods involve calculating when or at what point the prefetching should cease and a seek should be initiated ... | 01/15/2002 |
| 6332180 | Method and apparatus for communication in a multi-processor computer system Multiple instances of operating systems execute cooperatively in a single multiprocessor computer wherein all processors and resources are electrically connected together. The single physical machine with multiple physical processors and resources is subd... | 12/18/2001 |
| 6327645 | Cache memory system with memory request address queue, cache write address queue, and cache read address queue A cache memory system includes a main memory controller for retrieving memory data from a main memory unit, a cache memory for writing the memory data retrieved by the main memory controller therein, and a tag memory module for detecting presence of a cac... | 12/04/2001 |
| 6324636 | Memory management system and method The memory management system (20) includes a transform generator (22) capable of generating an address (28) and a confirmer (30) from a key. A controller (24) is connected to the transform generator (22) and sends the key to the transform generator (22) a... | 11/27/2001 |
| 6321298 | Full cache coherency across multiple raid controllers A method for providing cache coherency in a RAID system in which multiple RAID controllers provide read/write access to shared storage devices for multiple host computers. Each controller includes read, write and write mirror caches and the controllers an... | 11/20/2001 |
| 6321319 | Computer system for allowing a two word jump instruction to be executed in the same number of cycles as a single word jump instruction A system for allowing a two word jump instruction to be executed in the same number of cycles as a single word jump instruction, thereby allowing a processor system to increase memory space without reducing performance. A first address bus is coupled to t... | 11/20/2001 |
| 6317816 | Multiprocessor scaleable system and method for allocating memory from a heap The present invention is a method of allocating memory storage in a memory storage space commonly shared by multiple processors. The method allocates a minimum apparent memory storage space equal to one cache line and in response to storing an object, sai... | 11/13/2001 |
| 6314501 | Computer system and method for operating multiple operating systems in different partitions of the computer system and for allowing the different partitions to communicate with one another through shared memory A computer system comprises a plurality of processing modules that can be configured into different partitions within the computer system, and a main memory. Each partition operates under the control of a separate operating system. At least one shared mem... | 11/06/2001 |
| 6301649 | Semiconductor circuit with address translation circuit that enables quick serial access in row or column directions In a semiconductor memory, memory banks each having memory cells are arranged in X and Y directions. Each of the memory banks include a Y decoder for selecting Y-direction addresses of the memory cells and an X decoder for selecting X-direction addresses ... | 10/09/2001 |
| 6289427 | Controlling a read address or a write address based on the quantity of data read from or written into a memory Even if the timing of reading or writing the data of a predetermined quantity deviates, missing data can be minimized. The data quantity read from memory which stores the predetermined numbers of the fixed-length data is detected, the data quantity detect... | 09/11/2001 |
| 6286083 | Computer system with adaptive memory arbitration scheme A computer system includes an adaptive memory arbiter for prioritizing memory access requests, including a self-adjusting, programmable request-priority ranking system. The memory arbiter adapts during every arbitration cycle, reducing the priority of any... | 09/04/2001 |
| 6286097 | Computer chipset for accessing a conventional read only memory (ROM) A computer chipset having reduced peripheral pins for accessing a conventional ROM in a computer system is disclosed. There is a switching circuit within the chipset. When the computer is turned on, a booting control circuit activates a booting enabling s... | 09/04/2001 |
| 6282607 | Efficient scheduling of reading data from multiple storage mediums to satisfy multiple requests A dynamic process for improving the performance of a tape-based storage system is disclosed which takes a global view with regard to scheduling and tape selection. All requested data blocks located on multiple tapes within the storage system are analyzed ... | 08/28/2001 |
| 6282626 | No stall read access-method for hiding latency in processor memory accesses The memory space accessible by a processor is partitioned such that multiple memory regions map to the same physical memory. Processor accesses in one of the regions are regarded as normal accesses, and are satisfied from the memory or a read buffer. If m... | 08/28/2001 |
| 6279071 | System and method for column access in random access memories A column access system is provided with a column counter for producing a column address in response to an external address. The column address is latched in an address decoder which decodes the column address to select a column in the DRAM. A command deco... | 08/21/2001 |
| 6275900 | Hybrid NUMA/S-COMA system and method A hybrid non-uniform-memory-architecture/simple-cache-only-memory-architecture (NUMA/S-COMA) memory system and method are described useful in association with a computer system having a plurality of nodes coupled to each other. The plurality of nodes... | 08/14/2001 |
| 6272614 | Processing method and apparatus involving a processor instruction using hashing A program-controlling processing unit executes instructions stored in memory. A special instruction type is provided for selectively retrieving an element from memory in dependence on the value of input data subject of the instruction. Each instruction of... | 08/07/2001 |
