| Patent No. | Patent Title: |
| 6526488 | Computer systems |
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| 6430653 | Disk control unit and method for prefetching according to partiti... |
| 6430660 | Unified memory hard disk drive system |
| 6418525 | Method and apparatus for reducing latency in set-associative cach... |
| 6412041 | Real time processing method of a flash memory |
| 6408370 | Storage system assuring data integrity and a synchronous remote d... |
| 6405294 | Data center migration method and system using data mirroring |
| 6401186 | Continuous burst memory which anticipates a next requested start ... |
| 6397299 | Reduced latency memory configuration method using non-cacheable m... |
| 6397313 | Redundant dual bank architecture for a simultaneous operation fla... |
| 6397318 | Address generator for a circular buffer |
| 6389521 | Data transfer control of a video memory having a multi-divisional... |
| 6385672 | System to optimize packet buffer utilization via selectively part... |
| 6385699 | Managing an object store based on object replacement penalties an... |
| 6385640 | Switching apparatus applied to a plurality of information process... |
| 6381682 | Method and apparatus for dynamically sharing memory in a multipro... |
| 6378054 | Data backup device and method for use with a computer, and c... |
| 6374342 | Translation lookaside buffer match detection using carry of lower... |
| 6370620 | Web object caching and apparatus for performing the same |
| 6356990 | Set-associative cache memory having a built-in set prediction arr... |
| 6356974 | Architecture for state machine for controlling internal operation... |
| 6349376 | Method for decoding addresses using comparison with range previou... |
| 6339811 | Rotationally optimized seek initiation |
| 6332180 | Method and apparatus for communication in a multi-processor compu... |
| 6327645 | Cache memory system with memory request address queue, cache writ... |
| 6324636 | Memory management system and method |
| 6321298 | Full cache coherency across multiple raid controllers |
| 6321319 | Computer system for allowing a two word jump instruction to be ex... |
| 6317816 | Multiprocessor scaleable system and method for allocating memory ... |
| 6314501 | Computer system and method for operating multiple operating syste... |
| 6301649 | Semiconductor circuit with address translation circuit that enabl... |
| 6289427 | Controlling a read address or a write address based on the quanti... |
| 6286083 | Computer system with adaptive memory arbitration scheme |
| 6286097 | Computer chipset for accessing a conventional read only memory (R... |
| 6282607 | Efficient scheduling of reading data from multiple storage medium... |
| 6282626 | No stall read access-method for hiding latency in processor memor... |
| 6279071 | System and method for column access in random access memories |
| 6275900 | Hybrid NUMA/S-COMA system and method |
| 6272614 | Processing method and apparatus involving a processor instruction... |
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