Did You Know...
...that the Eveready Battery began as an invention called the "electric flowerpot," which was a tube with a battery and light bulb inside? The idea was to fasten this gizmo to the side of a flowerpot so it would illuminate the flowers from the bottom. The idea died on the vine and the businessman who licensed the flower pot, Conrad Huber, was left with a pile of useless tubes -- until he found a way to market them as batteries to light the world!
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| Number | Title | Issue Date |
| 5617555 | Burst random access memory employing sequenced banks of local tri-state drivers A burst dynamic random access memory (DRAM) (10) is disclosed having memory cells arranged in a number of quadrants (22), each quadrant including local I/O lines (24) for accessing the memory cells therein. The local I/O lines (24) of each quadrant are co... | 04/01/1997 |
| 5603005 | Cache coherency scheme for XBAR storage structure with delayed invalidates until associated write request is executed A method and apparatus for identifying obsolete data within cache memory in a multiprocessor architecture. This is accomplished while still providing the advantages of having cache resources dedicated to individual instruction processors as well as shared... | 02/11/1997 |
| 5586301 | Personal computer hard disk protection system The personal computer hard disk protection system is designed to protect data stored on computer hard disks while permitting multiple user operation. The personal computer hard disk protection system prevents unauthorized access to the hard-disk controlle... | 12/17/1996 |
| 5539898 | Data-array processing system wherein parallel processors access to the memory system is optimized A data array processing system comprises a memory system for storing an array of data elements and addressable by a single address, a plural number N of processors (PROC(0)-(15)) capable of processing data elements in parallel, and an address bus. In orde... | 07/23/1996 |
| 5539893 | Multi-level memory and methods for allocating data most likely to be used to the fastest memory level The present invention provides a multi-level memory system with a multi-level memory structure and methods for allocating data among the levels of memory based on the likelihood of imminent future use. The multi-level memory structure includes a first lev... | 07/23/1996 |
| 5537570 | Cache with a tag duplicate fault avoidance system and method A method for avoiding a tag duplicate fault. The method includes the steps of using a master - slave tag; selecting a first tag as a master and a second tag as a slave; inhibiting the second tag from initiating a hit signal when the first tag is set for a... | 07/16/1996 |
| 5537576 | Expandable memory for a digital signal processor including mapped first and second memory banks forming a continuous and contiguous address space A data processing and addressing unit for processing a set of either first or second type instructions having associated therewith operands stored in a single memory bank and operands stored in two memory banks, respectively. First and second memory banks... | 07/16/1996 |
| 5537577 | Interleaved memory wherein plural memory means comprising plural banks output data simultaneously while a control unit sequences the addresses in ascending and descending directions An interleaving memory system having a first memory device including a 0-bank and a 1-bank for simultaneously outputting data at even-numbered addresses from the 0-bank and data at odd-numbered addresses from the 1-bank, a second memory device including a... | 07/16/1996 |
| 5535366 | Method of and circuit arrangement for freeing communications resources, particularly for use by a switching element A buffer or other communications resource in, e.g., an ATM switch element receives random data which is then used by different data sinks. After the data has been outputted to the data sinks, the communications resource (e.g., the memory locations of the ... | 07/09/1996 |
| 5535362 | Data transfer control apparatus wherein a time value is compared to a clocked timer value with a comparison of the values causing the transfer of bus use right To change the priority order of a DMA transfer circuit and a CPU for the bus use right in a data processing system comprising the DMA transfer circuit, when an overflow occurs in the DMA transfer timer during DMA transfer, a request signal for shifting th... | 07/09/1996 |
| 5530938 | Non-volatile memory card device having flash EEPROM memory chips with designated spare memory chips and the method of rewriting data into the memory card device A memory card device and method of rewriting the same which require no separate memory for saving all data in a chip containing data to be rewritten, and in which data are not lost due to a power source failure that may occur during writing operation. Eac... | 06/25/1996 |
| 5530876 | Floppy disk controller incorporating standby signal generating functions for moving the control from an operational mode to a standby mode if predetermined drive conditions exist A floppy disk controller connected between a host system and several floppy disk units has a control circuit, a control register, and a standby control signal generating circuit. The control circuit is connected between the host system and the floppy disk... | 06/25/1996 |
| 5530836 | Method and apparatus for multiple memory bank selection In one aspect a memory bank selection system includes two asynchronous RAS pins and a single CAS pin, a switching circuit for each memory bank and a bank address decoder with an output to each switching circuit. The RAS pins are available to all of the sw... | 06/25/1996 |
| 5528768 | Multiprocessor communication system having a paritioned main memory where individual processors write to exclusive portions of the main memory and read from the entire main memory A communication system which makes possible a very fast data exchange between connected stored program controls, which is important especially for the control of industrial processes. A total storage area is subdivided into partial storage areas, which ar... | 06/18/1996 |
| 5526509 | Method and apparatus for controlling one or more hierarchical memories using a virtual storage scheme and physical to virtual address translation A processing apparatus of an integrated circuit structure for a multiprocessor system includes an execution unit operative on the basis of a virtual storage scheme and a cache memory having entries designated by logical addresses from the execution unit. ... | 06/11/1996 |
| 5526512 | Dynamic management of snoop granularity for a coherent asynchronous DMA cache A system and method dynamically changes the snoop comparison granularity between a sector and a page, depending upon the state (active or inactive) of a direct memory access (DMA) I/O device which is writing to a device on the system bus asynchronously wh... | 06/11/1996 |
| 5524230 | External information storage system with a semiconductor memory To provide an external storage system using a semiconductor memory in which the data reading and writing between the host CPU can be processed faster than the conventional magnetic disk, and only a particular sector is not frequently written and erased so... | 06/04/1996 |
| 5524233 | Method and apparatus for controlling an external cache memory wherein the cache controller is responsive to an interagent communication for performing cache control operations A cache control method and mechanism for an external cache memory having multiple cache lines using interagent communications to cause invalidating the external cache memory, flushing the external cache memory and/or changing the coherency state of lines ... | 06/04/1996 |
| 5519842 | Method and apparatus for performing unaligned little endian and big endian data accesses in a processing system A system which is able to perform unaligned big endian and little endian accesses to memory with little or no added overhead to the system. In the preferred embodiment, the processor operates in little endian data format. The memory, however, can store da... | 05/21/1996 |
| 5517633 | System for controlling an internally-installed cache memory A cache uses A bits of an offset portion which are not subjected to the address translation of the logical address and B bits of the portion other than the offset portion, which are subjected to an address translation. It has an address monitor portion ha... | 05/14/1996 |
| 5506976 | Branch cache A pipeline processor 2 having an associated branch cache 4 is provided. Each cache line 12 of the branch cache stores a cache TAG, a next branch data value R, a target address value TA and a target instruction value TI. The next branch data value indicate... | 04/09/1996 |
| 5506978 | Memory apparatus including a shift circuit for shifting a word select signal by a predetermined number of words A memory apparatus and a data processor using the same, wherein a shift circuit 12 which shifts a word select signal generated by an address decoder 11 by a predetermined number of words and gives it to a memory when a predetermined signal is given from t... | 04/09/1996 |
| 5504873 | Mass data storage and retrieval system A plurality of data storage modules form a library, with a directory archive maintaining a directory of the information contained on each data storage module (file server application) or on the storage modules retained in the library (volume server applic... | 04/02/1996 |
| 5504872 | Address translation register control device in a multiprocessor system A multiprocessor system address translation register control device that creates a directory for the handling of various address translation registers, wherein the directory retains processor data indicative of which of a plurality of address translation ... | 04/02/1996 |
| 5502832 | Associative memory architecture An association memory which permits the execution of all kinds of comparative operations. The associative memory includes a memory map (1) in which a search argument, which has been processed in a scanning module (3) and a masking unit (5,7), is compared ... | 03/26/1996 |
| 5502833 | System and method for management of a predictive split cache for supporting FIFO queues A first-in, first-out queue is implemented on two memory elements by enqueuing and dequeuing items from a first memory element and by swapping middle portions of the queue between the first memory element and the second memory whenever the first memory el... | 03/26/1996 |
| 5500950 | Data processor with speculative data transfer and address-free retry A data processor with speculative data transfer has address circuitry (40) and data circuitry (42, 44). The address circuitry generates a memory address associated with a data block and with a tag. The tag is representative of the validity of the data blo... | 03/19/1996 |
| 5499355 | Prefetching into a cache to minimize main memory access time and cache size in a computer system A cache subsystem for a computer system having a processor and a main memory is described. The cache subsystem includes a prefetch buffer coupled to the processor and the main memory. The prefetch buffer stores a first data prefetched from the main memory... | 03/12/1996 |
| 5497474 | Data stream addressing A number of memory locations are reserved in computer memory to store pointers which indicate an address within streams of sequentially arranged data. The data stream to be scanned is selected. To scan the information stored within the data stream, a sing... | 03/05/1996 |
| 5497478 | Memory access system and method modifying a memory interleaving scheme so that data can be read in any sequence without inserting wait cycles A memory access system and method is provided to modify a memory interleaving scheme so that data can be read from a memory system in any sequence without inserting a waiting cycle. Even addressees are assigned to a first memory bank and odd addresses to ... | 03/05/1996 |
| 5493664 | Microcomputer that transfers address and control to a debugging routine when an input address is a breakpoint address and a user accessible register for signalling if the breakpoint address is from the cache memory or a main memory A processor according to the present invention includes a user-accessible 1 bit register for indicating, upon instruction breaking or data breaking occurring, whether any instruction or data to be debugged is existent in a cache memory or in a memory, and... | 02/20/1996 |
| 5491809 | Smart erase algorithm with secure scheme for flash EPROMs A method for erasing blocks of a non-volatile memory includes detecting whether a block is in at least one of an erased state or a state secured from erasure; then setting a flag register at a first level for each block detected to be in at least one of a... | 02/13/1996 |
| 5491811 | Cache system using mask bits to recorder the sequences for transfers of data through cache to system memory Apparatus and method for improving the rate of transfer of data in the context of a system memory operated in conjunction with a cache. In one form, mask bits in a mask bit register are associated to bytes of cache. The mask bits are changed in state when... | 02/13/1996 |
| 5490265 | Late cancel method and apparatus for a high performance microprocessor system A late cancel method and apparatus for a high performance microprocessor system is disclosed. The invention is advantageously utilized in a microprocessor system comprising a processor, an external cache memory and a main memory. The processor incorporate... | 02/06/1996 |
| 5487160 | Concurrent image backup for disk storage system A disk drive within a disk array is utilized to capture the original image of data blocks that are updated, i.e., written over, through normal array processes during backup operations. The method captures original data images in a manner that allows the a... | 01/23/1996 |
| 5485598 | Redundant disk array (raid) system utilizing separate cache memories for the host system and the check data A memory device with a redundant disk array. In order to quicken the processing of data writing into the redundant disk array, a first cache memory for accessing the redundant disk array, a second cache memory for storing old data of the first cache memor... | 01/16/1996 |
| 5485591 | Microprocessor wherein the number of register output signal liner connected to the buses are reduced reducing the load capacity of the buses A microprocessor includes a plurality of registers connected to a plurality of buses. Selectors each select one of output signals of the registers to output the selected one of the output signals to one of the buses. The number of the register output sign... | 01/16/1996 |
| 5485597 | A CCD array memory device achieving high speed accessing by writing and reading data through a cache memory A memory device for storing analog or multilevel data which is easy to produce and of a small scale. The memory device according to the present invention circulates data between a plurality of linear CCD arrays which store data as electrical charges, allo... | 01/16/1996 |
| 5481689 | Conversion of internal processor register commands to I/O space addresses A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. Macroinstruction pipelining is employed (instead of microinstruction pipelining), with queuing between units of the CPU to allow flexibility in in... | 01/02/1996 |
| 5479641 | Method and apparatus for overlapped timing of cache operations including reading and writing with parity checking A cache circuit for a computer microprocessor and a method for performing cache operations (e.g., read and write) in a single, short cycle using overlapped clocking. The cache includes a tag array, a status array, and a data array. Parity information is g... | 12/26/1995 |
