Did You Know...
...that several people are credited with the invention of the flush toilet? Most people have heard of Thomas Crapper (1837-1910), the sanitary engineer who invented the valve-and-siphon arrangement that made the modern toilet possible. Another claimant to "the throne" was British inventor Alexander Cumming who patented a toilet in 1775. Then there's a nameless Minoan (a native of ancient Crete) who lived 4,000 years ago who supposedly was ahead of his time and created the first flush toilet!
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| Number | Title | Issue Date |
| 4949247 | System for transferring multiple vector data elements to and from vector memory in a single operation Apparatus for performing vector operations on the data elements of vectors includes a vector processor for performing arithmetic operations on the elements, a vector memory for storing the data elements for use by the processor, the vector memory having a... | 08/14/1990 |
| 4924376 | System for dynamically adjusting the accumulation of instructions in an instruction code prefetched pipelined computer An instruction code access control system used in an instruction code prefetched computer system includes at least an instruction buffer for accumulating prefetched instruction codes, and a data path switch for selectively coupling the instruction buffer ... | 05/08/1990 |
| 4914586 | Garbage collector for hypermedia systems A database of interests is maintained in a distributed computing system to register the individual interests of users in centrally stored non-textual media files, such as digital voice, music, scanned-in image, and video files. Uniquely named piece table ... | 04/03/1990 |
| 4888685 | Data conflict prevention for processor with input/output device A computer and an input/output device are connected via an interface bus. The input/output device has registers. The computer and the input/output device operate upon the basis of a pair of clock signals. When the input/output device accesses the register... | 12/19/1989 |
| 4868738 | Operating system independent virtual memory computer system An improved virtual memory computer system comprising a main processing unit for executing application and operating system software without virtual memory code and independently of virtual memory operation. A dedicated second processing unit is provided ... | 09/19/1989 |
| 4862347 | System for simulating memory arrays in a logic simulation machine A method and apparatus for simulating memory devices in a logic simulation machine include a finite state machine (FSM) having input/output (I/O) sources, instruction storage resources, a real memory resource, and instruction execution resources. A plural... | 08/29/1989 |
| 4847756 | Data transmission system for a computer controlled copying machine having master and slave CPU's A data transmission system includes a host CPU having an output terminal for repeatedly producing a predetermined number of data blocks in a predetermined sequence in a repeated manner. Each data block is defined by a sequence code for identifying each da... | 07/11/1989 |
| 4843593 | Word processor with decorative character printer A word processor for setting print out format for each line of a document to be printed by a decorative character printer. The word processor can format data by using various format data bits. The decorative character printer uses decorative character fon... | 06/27/1989 |
| 4841437 | System architecture for a test apparatus having primary and dependent processors A multifunction test apparatus which is capable of performing total communication network measurments and includes a primary processor linked to a number of dependent processors. The primary processor plays a number of different roles in the functioning o... | 06/20/1989 |
| 4839799 | Buffer control method for quickly determining whether a required data block is in the buffer In an information processing method and system including a secondary storage, a primary storage for storing data blocks of the secondary storage and a directory containing control information for the data blocks stored in the primary storage, the director... | 06/13/1989 |
| 4837740 | Asynchronous first-in-first-out register structure An asynchronous FIFO incorporates a series of interconnected cells alternately oppositely inverted to provide forward and retrograde data paths, so as to selectively establish virtual flip flops as needed at interfaces between cells. Each cell combines an... | 06/06/1989 |
| 4837676 | MIMD instruction flow computer architecture A computer which achieves highly parallel execution of programs in instruction flow form, as distinguished from data flow form employing a unique computer architecture in which the individual units such as, process control units, programmable function uni... | 06/06/1989 |
| 4833603 | Apparatus and method for implementation of a page frame replacement algorithm in a data processing system having virtual memory addressing In a multiprocessor, multiprogrammed data processing system employing virtual addressing, apparatus and method are provided for selecting a page frame in a main memory unit to be replaced by a new page frame of logic signal groups required by a processor.... | 05/23/1989 |
| 4831541 | System for editing real and virtual storage and secondary storage media An editing system for use in a virtual machine environment in which two virtual machines having corresponding virtual storage areas are operatively related to one another. The editing system allows a first virtual machine to print, display, modify and oth... | 05/16/1989 |
| 4829427 | Database query code generation and optimization based on the cost of alternate access methods An optimizer-code generator for use in a data base system. The optimizer-code generator employs a component called a scan analyzer for performing implementation-dependent analysis and providing implementation-dependent query code. The optimizer-code gener... | 05/09/1989 |
| 4827400 | Segment descriptor present bit recycle and detect logic for a memory management unit A data processing system includes a logical address to a physical address translator in an extended memory management unit. A 128 word memory stores task segment descriptor words which include a base address. A 16 word memory stores corresponding present ... | 05/02/1989 |
| 4827403 | Virtual processor techniques in a SIMD multiprocessor array A virtual processor mechanism and specific techniques and instructions for utilizing such virtual processor mechanism within an SIMD computer having numerous processors, and each physical processor having dedicated memory associated therewith. Each physic... | 05/02/1989 |
| 4825402 | Multiconfigurable interface driver/receiver circuit for a computer printer peripheral adaptor A single interface circuit for use with a computer peripheral having drivers and receivers which may be configured to be compatible with either short line input/output cables or long line input/output cables. Jumpers are provided to configure the interfac... | 04/25/1989 |
| 4823311 | Calculator keyboard with user definable function keys and with programmably alterable interactive labels for certain function keys Calculator having a keyboard in which one or more keys have labels created by a display and subject to changing interactively as the user desires. Typically, advanced scientific-programmable calculators may have too many functions to be adequately include... | 04/18/1989 |
| 4819164 | Variable frequency microprocessor clock generator A microprocessor based system (10) includes a central processing unit (CPU) (12) that controls the operation of a display (20) through a controller (22). System storage is provided with a read only memory (16) and random access memory (14). A reference cl... | 04/04/1989 |
| 4817002 | Electronic postage meter non-volatile memory systems having human visually readable and machine stored data A computing system having a non-volatile memory with locations with store data and are physically accessible such that the locations can be human visually readable to determine the data values stored therein. The non-volatile memory is operatively coupled... | 03/28/1989 |
| 4809216 | Print engine data interface A print engine data interface for sequentially accessing locations in a full page bit map for either retrieving the data therein and forwarding it to a print engine for subsequent printing, or for issuing a refresh command to refresh the data. A bit map a... | 02/28/1989 |
| 4809169 | Parallel, multiple coprocessor computer architecture having plural execution modes A coprocessor architecture specifically adapted for parallel operation as one of an array of coprocessors is described. Each of the coprocessors of the array are commonly responsive to a host processor. The coprocessor architecture preferably includes a s... | 02/28/1989 |
| 4807110 | Prefetching system for a cache having a second directory for sequentially accessed blocks A prefetching mechanism for a system having a cache has, in addition to the normal cache directory, a two-level shadow directory. When an information block is accessed, a parent identifier derived from the block address is stored in a first level of the s... | 02/21/1989 |
| 4807142 | Screen manager multiple viewport for a multi-tasking data processing system A task control structure for transferring tasks from a storage device to a system memory and for controlling execution of tasks, and a document manager for loading document information in the form of document data structures from the storage device to the... | 02/21/1989 |
| 4807115 | Instruction issuing mechanism for processors with multiple functional units An instruction issuing mechanism for boosting throughput of processors with multiple functional units. A Dispatch Stack (DS) and a Precedence Count Memory (PCM) are employed which allow multiple instructions to be issued per machine cycle. Additionally, i... | 02/21/1989 |
| 4806916 | Computer display with two-part cursor for indicating loci of operation A system for creating and modifying strings of symbols in a computer storage apparatus includes a two-part cursor for guiding the operator. One cursor part indicates the exact location where entered symbols will be inserted. A second cursor part highlight... | 02/21/1989 |
| 4799144 | Multi-function communication board for expanding the versatility of a computer A single board multiple option card for expanding the versatility of a host computer includes an onboard microprocessor, a digital signal processor and a switched memory device. The switched memory is accessible by the onboard microprocessor and the digit... | 01/17/1989 |
| 4797814 | Variable address mode cache A data processing system which contains a multi-level storage hierarchy, in which the two highest hierarchy levels (e.g. L1 and L2) are private (not shared) to a single CPU, in order to be in close proximity to each other and to the CPU. Each cache has a ... | 01/10/1989 |
| 4797812 | System for continuous DMA transfer of virtually addressed data blocks A channel apparatus including a transfer controller responsive to an input data transfer command, for translating virtual block address data designated by a channel command word (CCW) into RBA data to store the translated RBA data. The CCW commands the DM... | 01/10/1989 |
| 4794524 | Pipelined single chip microprocessor having on-chip cache and on-chip memory management unit A 32-bit central processing unit having a six-stage pipeline architecture with a cache memory and memory management unit all provided on a single integrated circuit (I.C.) chip but without any peripheral interface input/output circuits, clock or similar c... | 12/27/1988 |
| 4792920 | Interface providing impedance matching by selective connection of a resistor array to a power supply An interface system having a plurality of signal lines connected between a plurality of input terminals of a control circuit and a plurality of output terminals of a host computer. A plurality of resistor elements each have one end connected to a correspo... | 12/20/1988 |
| 4792892 | Data processor with loop circuit for delaying execution of a program loop control instruction A data processor for executing a program of instructions stored in a program memory controlled by a program counter. To execute a loop control instruction, calling for repeated execution N times of a sequence of "i" instructions, the processor includes a ... | 12/20/1988 |
| 4792896 | Storage controller emulator providing transparent resource sharing in a computer system A microprocessor controlled mass storage controller is used as an interface for mass storage devices which are shared by a plurality of stand-alone microcomputer systems. The microprocessor controlled mass storage controller has a system interface which m... | 12/20/1988 |
| 4791565 | Apparatus for controlling the use of computer software Apparatus for controlling the use of software in accordance with authorized software license limits, including a limit of the number of concurrent usages of a particular software in a computer system having one or more operator terminals and a central pro... | 12/13/1988 |
| 4791557 | Apparatus and method for monitoring and controlling the prefetching of instructions by an information processing system An information processing system includes a processor responsive to instructions for performing operations. The processor includes instruction queue for fetching and storing instructions in advance of execution and the system is responsive to certain of t... | 12/13/1988 |
| 4788639 | Frequency-coded multi-level interrupt control system for a multiprocessor system A multi-level priority interrupt system is used for controlling the access of input/output control devices to a host computer which is connected to the devices and controls their operation. The input/output control devices each of which is contained on a ... | 11/29/1988 |
| 4782442 | Time-sharing computer system operable in a host TSS mode and a terminal TSS mode The present invention is directed to time-sharing computer system which includes a host computer system which operates in response to a host TSS command, a terminal computer system which is connected to the host computer system through a line and operates... | 11/01/1988 |
| 4777616 | Increased resolution logic analyzer using asynchronous sampling Techniques for a logic analyzer instrument that permit the acquisition of digital samples from a plurality of logic signals in a large mainframe computer, or other system under test, in a manner that the signals can be reconstructed for viewing and analys... | 10/11/1988 |
| 4775954 | Apparatus for generating timing signals used for testing ICs having two enable input terminals A timing signal generating apparatus is used for testing ICs, particularly ICs having more than two enable input terminals. Data representative of the time of occurrence of a timing signal with respect to a reference signal is stored in a memory. In a fir... | 10/04/1988 |
