| Patent No. | Patent Title: |
| 6009499 | Pipelined stack caching circuit |
| 6006305 | Method and architecture for non-sequentially programming one-time... |
| 5996049 | Cache-coherency protocol with recently read state for data and ... |
| 5974516 | Byte-writable two-dimensional FIFO buffer having storage location... |
| 5974507 | Optimizing a cache eviction mechanism by selectively introducing ... |
| 5956748 | Asynchronous, dual-port, RAM-based FIFO with bi-directional addre... |
| 5946714 | Semiconductor storage device utilizing address management tables ... |
| 5943689 | On-demand initialization of memory locations as they are requeste... |
| 5943684 | Method and system of providing a cache-coherency protocol for ... |
| 5937423 | Register interface for flash EEPROM memory arrays |
| 5937429 | Cache memory having a selectable cache-line replacement scheme us... |
| 5936925 | Information record medium, apparatus for recording the same and ... |
| 5930826 | Flash memory protection attribute status bits held in a flash mem... |
| 5930226 | Storage medium storing plural data of plural types in reproductio... |
| 5924118 | Method and system for speculatively sourcing cache memory data pr... |
| 5924116 | Collaborative caching of a requested object by a lower level node... |
| 5915264 | System for providing write notification during data set copy |
| 5913222 | Color correction method in a virtually addressed and physically i... |
| 5911148 | Automated message processing system configured for automated tape... |
| 5909700 | Back-up data storage facility incorporating filtering to select d... |
| 5909698 | Cache block store instruction operations where cache coherency is... |
| 5907862 | Method and apparatus for the sharing of a memory device by multip... |
| 5907857 | Refresh-ahead and burst refresh preemption technique for managing... |
| 5900009 | System and method for accessing records in a cache slot which are... |
| 5897658 | Method and apparatus for protecting portions of memory by providi... |
| 5893923 | Microcontroller utilizing a circuit to select during reset proces... |
| 5893137 | Apparatus and method for implementing a content addressable memor... |
| 5890195 | Dram with integral sram comprising a plurality of sets of address... |
| 5890204 | User controlled storage configuration using graphical user interf... |
| 5875454 | Compressed data cache storage system |
| 5860158 | Cache control unit with a cache request transaction-oriented prot... |
| 5860119 | Data-packet fifo buffer system with end-of-packet flags |
| 5860081 | Interfacing an L2 cache to a single bus having alternative protoc... |
| 5854943 | Speed efficient cache output selector circuitry based on tag comp... |
| 5845317 | Multi-way cache expansion circuit architecture |
| 5835953 | Backup system that takes a snapshot of the locations in a mass st... |
| 5835932 | Methods and systems for maintaining data locality in a multiple m... |
| 5829028 | Data cache configured to store data in a use-once manner |
| 5822755 | Dual usage memory selectively behaving as a victim cache for L1 c... |
| 5813039 | Guest execution control system, method and computer process for a... |