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| Number | Title | Issue Date |
| 5818748 | Chip function separation onto separate stacked chips The high-voltage drivers and decoders of a direct-write EEPROM memory array are separated from the word lines and placed onto separate stacked chips. The separate chips are stacked face-to-face, and force-responsive self-interlocking microconnectors are u... | 10/06/1998 |
| 5781499 | Semiconductor memory device The semiconductor memory device of the present invention is provided with at least: a first sync-signal generation circuit that generates and outputs a first sync-signal synchronized with any of a first clock inputted from the outside and a second and thi... | 07/14/1998 |
| 5774395 | Electrically erasable reference cell for accurately determining threshold voltage of a non-volatile memory at a plurality of threshold voltage levels A reference cell in a nonvolatile memory is electrically erasable and the electrically erasable character of the memory is exploited to expand the voltage range over which a differential amplifier is useful for sensing the state of a bit. Selected element... | 06/30/1998 |
| 5768194 | Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein A single chip semiconductor integrated circuit device having a central processing unit (CPU) and a flash memory which stores data to be processed by the CPU and which provides data to the CPU through the data bus in response to accessing instructions from... | 06/16/1998 |
| 5748533 | Read circuit which uses a coarse-to-fine search when reading the threshold voltage of a memory cell A read circuit includes a driver which changes a gate voltage of a memory cell and a sense circuit which identifies when the memory cell trips. The driver searches for the threshold voltage of the memory cell using stages which ramp up gate voltage and st... | 05/05/1998 |
| 5745411 | Semiconductor memory device A semiconductor memory device that permits the threshold voltage Vth of a cell transistor to be measured easily and inexpensively is provided. A semiconductor memory device 1 is provided, which has a plurality of cell transistors C for storing predetermin... | 04/28/1998 |
| 5732027 | Memory having selectable output strength An output buffer circuit of a semiconductor memory device can produce multiple output buffer drive strengths. An electronic system including a memory device in which such an output buffer circuit is implemented can include a mechanism for enabling the out... | 03/24/1998 |
| 5729504 | Continuous burst edo memory device An integrated circuit memory device is described which can operate at high data speeds. The memory device can either store or retrieve data from the memory in a burst access operation. The burst operations latch a memory address from external address line... | 03/17/1998 |
| 5721709 | Address decoder circuits adjusted for a high speed operation at a low power consumption A decoder circuitry is provided between input signal lines and word lines. The number of the word lines is larger than the input signal lines. The decoder circuitry comprises a plurality of stages including at least an input side stage adjacent to the inp... | 02/24/1998 |
| 5721707 | Erase voltage control circuit for an electrically erasable non-volatile memory cell An erase voltage control circuit for an electrically erasable non-volatile memory cell having a control electrode and a first electrode. The circuit includes negative voltage generator means for generating a negative erase voltage to be supplied to the co... | 02/24/1998 |
| 5717632 | Apparatus and method for multiple-level storage in non-volatile memories A storage control circuit determines a programmed threshold voltage VtP of a storage cell in which the transistor threshold voltages VtT of the cell may overlap while the logical threshold voltages VtL remain distinct. In ... | 02/10/1998 |
| 5708607 | Data read circuit of a memory A data read circuit of a memory includes an inverting unit, a precharging unit, a first amplifying unit, a second amplifying unit, and an output buffer unit. The inverting unit inverts data from a sense amplifier, and the precharging unit precharges a dat... | 01/13/1998 |
| 5708615 | Semiconductor memory device with reduced current consumption during precharge and reading periods A semiconductor memory device with low current consumption is disclosed. A bit line selecting circuit (3) establishes electrical connection between a bit line (BL) selected during a read period and a node (N2) in response to bit line connection/selection ... | 01/13/1998 |
| 5708599 | Semiconductor memory device capable of reducing power consumption A reference voltage generated in a Vref1 generating circuit is supplied from a corresponding applied voltage selector to respective backgates of access transistors in each SRAM cell constituting a column which is selected by a column decoder. On the other... | 01/13/1998 |
| 5706231 | Semiconductor memory device having a redundant memory cell NMOS transistors are arranged between bit lines included in a memory cell array and a node supplied with a power supply potential. The NMOS transistor corresponding to a defective column to be replaced with a redundant memory cell column is turned of in a... | 01/06/1998 |
| 5706241 | Eeprom semiconductor memory device including circuit for generating a voltage higher than a power supply voltage A semiconductor memory device comprising a memory cell array of a plurality of memory cells formed and arranged on either a semiconductor substrate or a well of a first conductivity type formed on said semiconductor substrate, a plurality of voltage gener... | 01/06/1998 |
| 5703826 | Video random access memory chip configured to transfer data in response to an internal write signal The invention is a monolithic video random access memory (VRAM) chip that has more than one write control pin which is used to segment the VRAM into banks or sub-chips having four DQ planes such that a nibble of data can be written to the VRAM. Using the ... | 12/30/1997 |
| 5703810 | DRAM for texture mapping A latch/mask mechanism that is located between the sense amplifiers of a DRAM and the data bus. The latch/mask mechanism decouples the data bus from the sense amplifiers and permits innovative, time saving functionality during read and write operations. D... | 12/30/1997 |
| 5703803 | Dynamically controlled, cross-stacked CAM cell A memory cell comprising a storage cell and a comparison circuit. The storage cell has a second node and a third node. The comparison circuit is coupled to the storage cell and comprises a first plurality of transistors coupled in series to a first input ... | 12/30/1997 |
| 5699297 | Method of rewriting data in a microprocessor additionally provided with a flash memory The present invention relates to a method of rewriting data in a microcomputer additionally provided with a flash memory having a refresh mode, in which the data retained in an area arbitrarily specified in the flash memory is transferred to a RAM for tem... | 12/16/1997 |
| 5699314 | Video random access memory device and method implementing independent two we nibble control The invention is a monolithic video random access memory (VRAM) chip that has more than one write control pin which is used to segment the VRAM into banks or sub-chips having four DQ planes such that a nibble of data can be written to the VRAM. Using the ... | 12/16/1997 |
| 5696731 | Semiconductor memory device using internal voltage obtained by boosting supply voltage A main booster circuit generates an internal supply voltage obtained by boosting a supply voltage. A detector detects a skew in an address signal. An oscillator generates a pulse signal while the detector is detecting the skew in the address signal. An au... | 12/09/1997 |
| 5694353 | Non-volatile ferroelectric memory device equipped with reference voltage generator for exactly regulating reference voltage to the mid point between two logic level and method of reading out data bit therefrom A non-volatile ferroelectric memory cell supplies electric charge from the ferroelectric capacitor to one of bit lines so as to rise the bit line to one of a first potential level representative of logic "1" level and a second potential level representati... | 12/02/1997 |
| 5694365 | Semiconductor memory device capable of setting the magnitude of substrate voltage in accordance with the mode A DRAM includes a substrate voltage generation unit for generating a substrate voltage having a negative value to be applied to a first node. The substrate voltage generation unit includes a detecting circuit. The detecting circuit includes a first PMOS t... | 12/02/1997 |
| 5694364 | Semiconductor integrated circuit device having a test mode for reliability evaluation In the normal mode, a first voltage-down converter down-converts an external power supply voltage to provide a large, first internal power supply voltage to the peripheral circuitry via a first internal power supply voltage supplying line, and a second vo... | 12/02/1997 |
| 5691935 | Memory element and method of operation thereof A memory element that includes a stored charge element coupled to a bi-directional voltage dropping element that exhibits substantially definite voltage drops when conducting in each direction is the basis for a family of memory cells and circuits. An ext... | 11/25/1997 |
| 5687118 | PMOS memory cell with hot electron injection programming and tunnelling erasing A P-channel MOS memory cell has P+ source and drain regions formed in an N-well. A thin tunnel oxide is provided between the well surface and an overlying floating gate. In one embodiment, the thin tunnel oxide extends over a substantial portion of the ac... | 11/11/1997 |
| 5684745 | SRAM device with a bit line discharge circuit for low power The present invention provides an SRAM device comprising a first discharger for discharging a first bit line at the write operation when the first bit line is at a low level; a second discharger for discharging a second bit line at the write operation whe... | 11/04/1997 |
| 5684746 | Semiconductor memory device in which a failed memory cell is placed with another memory cell A semiconductor memory device including a memory cell array having memory cells arranged in XY directions, means for storing at least X addresses of failure bit memory cells among memory cells defined by an X address and a Y address in the memory cell arr... | 11/04/1997 |
| 5684748 | Circuit for testing reliability of chip and semiconductor memory device having the circuit A test circuit shortens test time during testing reliability of a chip. The test circuit comprises a bit line level sensing circuit connected to a bit line and transferring data in response to a voltage level of the data when a memory cell data is transfe... | 11/04/1997 |
| 5682354 | CAS recognition in burst extended data out DRAM An integrated memory circuit is described which can be operated in a burst access mode. The memory circuit includes an address counter which changes column addresses in one of a number of predetermined patterns. The memory includes generator circuit for g... | 10/28/1997 |
| 5682353 | Self adjusting sense amplifier clock delay circuit A clock delay circuit for generating a delay for a sense amplifier release signal in an integrated circuit semiconductor memory device is disclosed. Rather than utilize traditional programmable capacitors that must be trimmed on a die by die basis, the no... | 10/28/1997 |
| 5675537 | Erase method for page mode multiple bits-per-cell flash EEPROM An improved erasing structure for performing a programming back operation and a concurrent verify operation subsequent to application of an erasing pulse in an array of multiple bits-per-cell flash EEPROM memory cells is provided. A memory core array (12)... | 10/07/1997 |
| 5673233 | Synchronous memory allowing early read command in write to read transitions A synchronous random access memory, such as a synchronous dynamic random access memory or a synchronous graphic random access memory, is responsive to command signals and includes a bank memory array. A command decoder/controller responds to command signa... | 09/30/1997 |
| 5671186 | Semiconductor memory device having bit line precharger A semiconductor memory device includes a bit line, a memory cell, and a precharge circuit responsive to a precharge signal for charging the bit line. The precharge circuit is enabled before cell data is read from the memory cell via the precharged bit lin... | 09/23/1997 |
| 5668754 | Ferroelectric memory cell and reading/writing method thereof A ferroelectric memory cell is provided, which enables to store a plurality of data values therein, and writing and reading methods thereof. The memory cell is includes first to n-th ferroelectric capacitors connected in parallel where n is an integer gre... | 09/16/1997 |
| 5668756 | Multi-value level type non-volatile semiconductor memory unit and method of rewriting the same A non-volatile semiconductor memory unit comprises a memory cell having a semiconductor substrate, a control gate formed over the semiconductor substrate, an electric charge accumulative layer formed between the semiconductor substrate and the control gat... | 09/16/1997 |
| 5668769 | Memory device performance by delayed power-down The method of this invention prevents transient currents at high-frequency disable cycles and disables DC current paths after a minimum delay time, thereby reducing power dissipation. This invention includes a delay circuit functioning to prevent disablem... | 09/16/1997 |
| 5668759 | Method for erasing and verifying nonvolatile semiconductor memory In a nonvolatile semiconductor memory device including memory cells, a predetermined number of the memory cells are simultaneously erased. Only when at least one of the memory cells is overerased, i.e., is in a depletion state, a threshold voltage recover... | 09/16/1997 |
| 5666308 | Writing circuit for non-volatile memory A writing circuit for non-volatile memory capable of preventing the structure of the circuit from becoming complicated in an integrated circuit from the points of view of logic and layout by reducing the number of kinds of control signal voltages. The cir... | 09/09/1997 |
