| Patent No. | Patent Title: |
| 5818748 | Chip function separation onto separate stacked chips |
| 5781499 | Semiconductor memory device |
| 5774395 | Electrically erasable reference cell for accurately determining ... |
| 5768194 | Data line disturbance free memory block divided flash memory and ... |
| 5748533 | Read circuit which uses a coarse-to-fine search when reading the ... |
| 5745411 | Semiconductor memory device |
| 5732027 | Memory having selectable output strength |
| 5729504 | Continuous burst edo memory device |
| 5721709 | Address decoder circuits adjusted for a high speed operation at a... |
| 5721707 | Erase voltage control circuit for an electrically erasable non-vo... |
| 5717632 | Apparatus and method for multiple-level storage in non-volatile m... |
| 5708607 | Data read circuit of a memory |
| 5708615 | Semiconductor memory device with reduced current consumption duri... |
| 5708599 | Semiconductor memory device capable of reducing power consumption |
| 5706231 | Semiconductor memory device having a redundant memory cell |
| 5706241 | Eeprom semiconductor memory device including circuit for generati... |
| 5703826 | Video random access memory chip configured to transfer data in re... |
| 5703810 | DRAM for texture mapping |
| 5703803 | Dynamically controlled, cross-stacked CAM cell |
| 5699297 | Method of rewriting data in a microprocessor additionally provide... |
| 5699314 | Video random access memory device and method implementing indepen... |
| 5696731 | Semiconductor memory device using internal voltage obtained by bo... |
| 5694353 | Non-volatile ferroelectric memory device equipped with reference ... |
| 5694365 | Semiconductor memory device capable of setting the magnitude of ... |
| 5694364 | Semiconductor integrated circuit device having a test mode for ... |
| 5691935 | Memory element and method of operation thereof |
| 5687118 | PMOS memory cell with hot electron injection programming and tunn... |
| 5684745 | SRAM device with a bit line discharge circuit for low power |
| 5684746 | Semiconductor memory device in which a failed memory cell is plac... |
| 5684748 | Circuit for testing reliability of chip and semiconductor memory ... |
| 5682354 | CAS recognition in burst extended data out DRAM |
| 5682353 | Self adjusting sense amplifier clock delay circuit |
| 5675537 | Erase method for page mode multiple bits-per-cell flash EEPROM |
| 5673233 | Synchronous memory allowing early read command in write to read ... |
| 5671186 | Semiconductor memory device having bit line precharger |
| 5668754 | Ferroelectric memory cell and reading/writing method thereof |
| 5668756 | Multi-value level type non-volatile semiconductor memory unit and... |
| 5668769 | Memory device performance by delayed power-down |
| 5668759 | Method for erasing and verifying nonvolatile semiconductor memory |
| 5666308 | Writing circuit for non-volatile memory |
Quotables 
PatentStorm News
