Bizarre Patents
Crispy Chip Sandwich and Process of Producing a Sandwich Product
A food product comprising a multilayer cookie or snack having outer layers formed from a crispy type edible food product such as a potato chip or corn chip, etc. with an intermediate marshmallow layer being in contact with the inner surface of each crispy chip and one or more filler substances.
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| Number | Title | Issue Date |
| 7587580 | Power efficient instruction prefetch mechanism A processor includes a conditional branch instruction prediction mechanism that generates weighted branch prediction values. For weakly weighted predictions, which tend to be less accurate than strongly weighted predictions, the power associating with speculatively ... | 09/08/2009 |
| 7464202 | Clock system for controlling autonomous transfer of data A system that controls the application of a clock signal used to autonomously transfer data from a remote device to a host device. The clock signal can be allowed to continually cycle for legacy applications, or can be controlled to only cycle when data transmission... | 12/09/2008 |
| 7461243 | Deferred branch history update scheme In one embodiment, a processor comprises a branch prediction array, an index generator coupled to the branch prediction array, and a control unit coupled to the index generator. The branch prediction array is configured to store a plurality of branch predictions for... | 12/02/2008 |
| 7461236 | Transferring data in a parallel processing environment An integrated circuit includes a plurality of tiles. Each tile comprises a processor; and a switch including switching circuitry to forward data over data paths from other tiles to the processor and to switches of other tiles according to a switch instruction indica... | 12/02/2008 |
| 7454596 | Method and apparatus for partitioned pipelined fetching of multiple execution threads Methods and apparatus for partitioning a microprocessor pipeline to support pipelined branch prediction and instruction fetching of multiple execution threads. A thread selection stage selects a thread from a plurality of execution threads. In one embodiment, storag... | 11/18/2008 |
| 7454594 | Processor for realizing software pipelining with a SIMD arithmetic unit simultaneously processing each SIMD instruction on a plurality of discrete elements A processor and its arithmetic instruction processing method and arithmetic operation control method are disclosed that add a new operand designation option to SIMD arithmetic instructions and permit software pipelining between arithmetic operations performed in par... | 11/18/2008 |
| 7454602 | Pipeline having bifurcated global branch history buffer for indexing branch history table per instruction fetch group A method and apparatus for updating global branch history information are disclosed. A dynamic branch predictor within a data processing system includes a global branch history (GBH) buffer and a branch history table. The GBH buffer contains GBH information of a gro... | 11/18/2008 |
| 7447881 | Branch prediction apparatus and method A branch prediction apparatus has a configuration such that a predicted branch target address and an offset are obtained by referring to a branch history, an instruction fetch address and the offset are added to obtain a branch instruction address, the branch instru... | 11/04/2008 |
| 7447882 | Context switching within a data processing system having a branch prediction mechanism A branch target buffer is provided which maintains its entries across context switches within a virtually addressed system. Branch mispredictions are detected for individual entries within the branch target buffer and those individual entries are invalidated. ... | 11/04/2008 |
| 7447885 | Reading prediction outcomes within a branch prediction mechanism A branch prediction mechanism includes a history value register storing a history value which is used to address into a history buffer from which a plurality of prediction values are read and stored into a prediction value store. The one or more prediction values to... | 11/04/2008 |
| 7447873 | Multithreaded SIMD parallel processor with loading of groups of threads In a multithreaded processing core, groups of threads are executed using single instruction, multiple data (SIMD) parallelism by a set of parallel processing engines. Input data defining objects to be processed received as a stream of input data blocks, and the inpu... | 11/04/2008 |
| 7444498 | Load lookahead prefetch for microprocessors The present invention allows a microprocessor to identify and speculatively execute future load instructions during a stall condition. This allows forward progress to be made through the instruction stream during the stall condition which would otherwise cause the m... | 10/28/2008 |
| 7441105 | Reducing multiplexer circuitry for operand select logic associated with a processor Methods and apparatus are provided for reducing the amount of resources allocated for handling multiplexing in a processor. Characteristics associated with processing blocks are analyzed. Operand restrictions and register groups can be configured to allow the use of... | 10/21/2008 |
| 7441100 | Processor synchronization in a multi-processor computer system A method for synchronizing a plurality of processors of a multi-processor computer system on a synchronization point is disclosed. The method includes triggering a first set of processors, using a lead processor of the plurality of processors when the lead processor... | 10/21/2008 |
| 7437541 | Atomically updating 64 bit fields in the 32 bit AIX kernel A method, system, and computer instructions for atomically updating 64-bit fields in the 32-bit AIX kernel, wherein the underlying hardware's 64-bit capable instructions are used to construct an atomic primitive. If a data request applies to the 32-bit kernel on 64-... | 10/14/2008 |
| 7437537 | Methods and apparatus for predicting unaligned memory access In an instruction execution pipeline, the misalignment of memory access instructions is predicted. Based on the prediction, an additional micro-operation is generated in the pipeline prior to the effective address generation of the memory access instruction. The add... | 10/14/2008 |
| 7437538 | Apparatus and method for reducing execution latency of floating point operations having special case operands An apparatus and method for floating-point special case handling. In one embodiment, a processor may include a first execution unit configured to execute a longer-latency floating-point instruction, and a second execution unit configured to execute a shorter-latency... | 10/14/2008 |
| 7434028 | Hardware stack having entries with a data portion and associated counter According to some embodiments, determining a new value to be pushed onto a hardware stack having n entries is determined. Each entry in the stack may include a data portion and an associated counter. If the new value equals the data portion of the entry associated w... | 10/07/2008 |
| 7434029 | Inter-processor control A system includes a first processor coupled to a second processor. The first and second processors are coupled to memory. The first processor fetches and executes supported instructions until an unsupported instruction is detected. The second processor executes the ... | 10/07/2008 |
| 7434040 | Copying of unaligned data in a pipelined operation Methods, computer readable media and computing devices including program instructions are provided for copying unaligned data. One method embodiment includes using 12 execution units to move 16 bytes of data from an unaligned data area to an aligned data area during... | 10/07/2008 |
| 7434035 | Method and system for processing instructions in grouped and non-grouped modes An embodiment of the invention is a processor for detecting one or more groups of instructions and initiating a processor action upon detecting one or more groups of instructions. The processor includes an instruction unit for fetching and decoding a group of instru... | 10/07/2008 |
| 7430656 | System and method of converting data formats and communicating between execution units A method and system including transmitting data in an architectural format between execution units in a multi-type instruction set architecture and converting data received in the architectural format to an internal format and data output in the internal format to t... | 09/30/2008 |
| 7430652 | Devices for performing multiple independent hardware acceleration operations and methods for performing same Multiple hardware accelerators can be used to efficiently perform processes that would otherwise be performed by general purpose hardware running software. The software overhead and bus bandwidth associated with running multiple hardware acceleration processes can b... | 09/30/2008 |
| 7430657 | System, method and device for queuing branch predictions A system, method and device for storing branch predictions in a queue that may be connected to a branch prediction unit, and for delivering the stored predictions to an instruction fetch unit. A look up may be made of for example two sequential lines, and for exampl... | 09/30/2008 |
| 7428632 | Branch prediction mechanism using a branch cache memory and an extended pattern cache A branch prediction mechanism includes a branch prediction memory and an extended pattern cache. The extended pattern cache detects predetermined repeating patterns of branch outcomes and stores a plurality of compressed representations of these such that when they ... | 09/23/2008 |
| 7426629 | Processing activity masking in a data processing system A data processing system is provided with mechanisms such that when a data value is stored within a data register, further data values are stored within one or more further registers such that the total number of signal transitions from high to low and from low to h... | 09/16/2008 |
| 7421565 | Method and apparatus for indirectly addressed vector load-add -store across multi-processors A method and apparatus to correctly compute a vector-gather, vector-operate (e.g., vector add), and vector-scatter sequence, particularly when elements of the vector may be redundantly presented, as with indirectly addressed vector operations. For an add operation, ... | 09/02/2008 |
| 7421568 | Power saving methods and apparatus to selectively enable cache bits based on known processor state A processor capable of fetching and executing variable length instructions is described having instructions of at least two lengths. The processor operates in multiple modes. One of the modes restricts instructions that can be fetched and executed to the longer leng... | 09/02/2008 |
| 7421570 | Method for managing a microprocessor stack for saving contextual data The present invention relates to a method for managing the stack of a microprocessor comprising a central processing unit and a memory array, the central processing unit comprising registers containing contextual data and a stack pointer, the stack being a zone of t... | 09/02/2008 |
| 7421567 | Using a modified value GPR to enhance lookahead prefetch The present invention allows a microprocessor to identify and speculatively execute future instructions during a stall condition. This allows forward progress to be made through the instruction stream during the stall condition which would otherwise cause the microp... | 09/02/2008 |
| 7421566 | Implementing instruction set architectures with non-contiguous register file specifiers There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code includes processing a fixed-width instruction of a fixed-width instruction ... | 09/02/2008 |
| 7418577 | Fail instruction to support transactional program execution One embodiment of the present invention provides a system that supports executing a fail instruction, which terminates transactional execution of a block of instructions. During operation, the system facilitates transactional execution of a block of instructions wit... | 08/26/2008 |
| 7418585 | Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts A multiprocessing system is disclosed. The system includes a multithreading microprocessor including a plurality of thread contexts (TCs), each having a program counter and a general purpose register set for executing a thread. The microprocessor also includes a sha... | 08/26/2008 |
| 7418584 | Executing system management mode code as virtual machine guest In one embodiment, a register in a processor is programmable with an intercept indication indicative of whether or not an event that would cause a transition by the processor to a first mode is to be intercepted during execution of a guest. Responsive to the interce... | 08/26/2008 |
| 7415600 | Microprocessor that carries out context switching by shifting context information stored in a ringed shift register A microprocessor includes a first ringed shift register having a plurality of registers storing a plurality of context information respectively, the registers being connected in a loop, an instruction decoder transmitting the context information to a reference regis... | 08/19/2008 |
| 7415597 | Processor with dependence mechanism to predict whether a load is dependent on older store A processor may include a scheduler configured to issue operations and a load store unit configured to execute memory operations issued by the scheduler. The load store unit is configured to store information identifying memory operations issued to the load store un... | 08/19/2008 |
| 7412586 | Switch memory architectures The present invention provides a switch memory architecture (SMA) consisting of: (i) processing elements (PE) (ii) memory banks (MB), and (iii) interconnect switches (ISWITCH). The present invention allows for efficient, potentially unbounded data transfer between t... | 08/12/2008 |
| 7412589 | Method to detect a stalled instruction stream and serialize micro-operation execution A computer implemented method, apparatus, and computer usable program code for ensuring forward progress of instructions in a pipeline of a processor. Instructions are received in the pipeline. Instruction flushes are counted in the pipeline to determine a flush cou... | 08/12/2008 |
| 7412593 | Processor for processing a program with commands including a mother program and a sub-program A processor for processing a program with commands, which has a mother program with a sub-program jump command and a sub-program, which is to be processed in response to the sub-program jump command. The processor has a command processor, which is adapted in the mot... | 08/12/2008 |
| 7406587 | Method and system for renaming registers in a microprocessor A processor includes an active list to buffer instructions and their associated condition codes for processing. A mapping table in the processor maps a logical register associated with the instruction to a selected one of a plurality of unique physical registers. Th... | 07/29/2008 |
