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| Number | Title | Issue Date |
| 4386401 | High speed processing restarting apparatus The present apparatus includes logic for stopping timing circuits in a central processing unit and for restarting the timing circuits to produce timing signals synchronized with an asynchronous external signal. The continuous running master clock of the c... | 05/31/1983 |
| 4382277 | Method and means utilizing multiple processing means for determining degree of match between two data arrays Method and apparatus are disclosed for determining a particular criterion value and an associated positional value for the degree of match between the juxtaposition of a plurality of events of a query and a plurality of corresponding events of a stored da... | 05/03/1983 |
| 4371924 | Computer system apparatus for prefetching data requested by a peripheral device from memory A computer system apparatus is disclosed for improved handling of requests by a peripheral device for data from memory. The apparatus serially receives multiple memory addresses from which data is requested by the peripheral device, and makes a determinat... | 02/01/1983 |
| 4371925 | Data processing system having unique bus control operation A data processing system using microcode architecture in which a two-level microcode system comprises one or more first, or "horizontal", microinstructions and a plurality of second, or "vertical", microinstruction portions in a vertical microcontrol stor... | 02/01/1983 |
| 4371926 | Input/output information indication system In data processing apparatus in which address and data are transferred by means of DMA through an address bus and a data bus, a coincidence circuit determines whether the address on the address bus coincides with an address designated by an address design... | 02/01/1983 |
| 4365290 | Computer system with power control circuit A digital computer system is described as comprising an input data circuit, a processor for executing a program stored in a memory to process the inputted data, a depletable energy source (e.g., a battery) for energizing the elements of the computer syste... | 12/21/1982 |
| 4356545 | Apparatus for monitoring and/or controlling the operations of a computer from a remote location Apparatus for monitoring and/or controlling the operations of a computer at a user site from a support center over a telephone line, the computer at the user site including a central processing unit (CPU) and a display terminal. The apparatus includes a t... | 10/26/1982 |
| 4355355 | Address generating mechanism for multiple virtual spaces The detailed embodiment associates access registers (AR's) with the general purpose registers (GPR's) in a data processor. The AR's are each loaded with a unique STD (segment table descriptor). The STD comprises a segment table address in main storage and... | 10/19/1982 |
| 4354231 | Apparatus for reducing the instruction execution time in a computer employing indirect addressing of a data memory Instructions which are read from a program memory of a control computer employing indirect addressing of a data memory are stored temporarily and sequentially in a buffer memory to form an execution queue. The absolute address to the data memory is genera... | 10/12/1982 |
| 4354227 | Fixed resource allocation method and apparatus for multiprocessor systems having complementarily phased cycles In multiprocessor data processing systems that utilize individual processors having interlaced cycles of operation controlled by complementarily phased clocks, contention for fixed resources such as memory, I/O, or data storage for example, may result unl... | 10/12/1982 |
| 4354230 | Synchronized, fail-operational, fail-safe multi-computer control system For each of two computer systems, logic flowcharts describe background program in which highly detailed memory checksum tests of fixed memory and complementary tests of variable memory are performed, the background program being interrupted for utility pr... | 10/12/1982 |
| 4354225 | Intelligent main store for data processing systems A data processing system comprising an active and intelligent main store including a main memory, a main store controller for accessing the main memory in a manner allowing different address and data structures, and a main store bus connected to the contr... | 10/12/1982 |
| 4349871 | Duplicate tag store for cached multiprocessor system A cached multiprocessor system operated in an ordered pipeline timing sequence in which the time slot for use of the cache is made long enough to permit only one cache access. Further, the time slot for data transfers to and from the processors succeeds t... | 09/14/1982 |
| 4348740 | Method and portable apparatus for comparison of stored sets of data Method and portable processor for storing and comparing sets of personal data relating to personal preferences and personality. First and second portable processing units each include a processor, a memory, an input device, a display device, and a connect... | 09/07/1982 |
| 4348722 | Bus error recognition for microprogrammed data processor An integrated circuit microprocessor includes storage means coupled to a control unit for receiving from the control unit information regarding how the next bus cycle is to be run. Upon receipt of a bus error signal from a peripheral device, the storage m... | 09/07/1982 |
| 4345315 | Customer satisfaction terminal An electronic terminal for electronically collecting opinion data from customers of a service organization as to the satisfaction with the services rendered. The electronic terminal has a keyboard that displays the inquiries with multiple choice responses... | 08/17/1982 |
| 4345245 | Method and apparatus for arranging segmented character groups in a digital typesetter A method for displaying characters on a raster display including the steps of storing a digitized font of normalized encoded characters in a first store, storing the identity size, and display location of the characters in a second store, generating a suc... | 08/17/1982 |
| 4344132 | Serial storage interface apparatus for coupling a serial storage mechanism to a data processor input/output bus Serial storage interface apparatus for coupling a serial storage mechanism, such as a charge coupled storage device or a magnetic bubble storage device, to a data processor input/output (I/O) bus. Speed control circuitry is provided for causing the serial... | 08/10/1982 |
| 4342097 | Memory buffer A memory buffer is provided between a receiving system and a digital computer to provide an indication of the number of times pulses from the same source have been received in a predetermined interval of time upon interrogation of the memory buffer by the... | 07/27/1982 |
| 4342082 | Program instruction mechanism for shortened recursive handling of interruptions Program instruction TPI (Test Pending Interruption) and associated data processor sequence controls for its execution enable interruption handling programs to operate in a shortened recursive mode relative to interruptions pending while such programs are ... | 07/27/1982 |
| 4342081 | Tape device adapter A tape device adapter logic control system is disclosed for accommodating the transfer of control information and data of variable formats, densities, and logic level conventions between a medium performance device controller (MPDC) and mass storage devic... | 07/27/1982 |
| 4340933 | Data processing system having centralized nonexistent memory address detection In a data processing system which includes a central processing unit (CPU) having one or more common buses to which one or more main memory units for storing program software instructions and program data are connected, logic is provided within the CPU fo... | 07/20/1982 |
| 4339804 | Memory system wherein individual bits may be updated A memory system having a word-addressable memory and bit changing circuitry for changing or updating individual bits within the data words stored in the memory. The memory includes a primary memory and a copy memory. The copy memory stores duplicates of t... | 07/13/1982 |
| 4339805 | Information recording system An information recording system is provided with a page buffer for storing one page information of those pieces of information supplied from an exterior information supplier. The information stored in the page buffer is read out character by character and... | 07/13/1982 |
| 4338599 | Apparatus for alpha-numeric/graphic display The computer system of this invention has, as the heart of the system, a simple processing unit for providing most data processing by the computer system under control of a read-only memory which contains only instructions and other data for the CPU. The ... | 07/06/1982 |
| 4336601 | Rewritable programmable logic array A Rewritable Programmable Logic Array (R-PLA) which can alter dynamically logic functions during processing by loading a word pattern of bit personalities to realize the specific logic functions into memory cells of Current Mode Logic (CML) is constructed... | 06/22/1982 |
| 4335426 | Remote processor initialization in a multi-station peer-to-peer intercommunication system For a system including a plurality of processors which are interconnected by a communications link through individual communication stations, a method of remote processor initialization is disclosed which provides a specific frame exchange procedure for t... | 06/15/1982 |
| 4335445 | System for interfacing computers with programmable power supplies Programmable power supplies as used in automatic testing systems (ATS) require three commands from a computer; namely, polarity, gain and analog magnitude. Whether received from a general purpose bus such as the IEEE 488 or other means the commands are in... | 06/15/1982 |
| 4333089 | Keyboard and control system The computer system of this invention has, as the heart of the system, a simple processing unit for providing most data processing by the computer system under control of a read-only memory which contains only instructions and other data for the CPU. The ... | 06/01/1982 |
| 4333144 | Task communicator for multiple computer system A task communicator for each computer in a multiple computer system is disclosed. The task communicator provides communication of data values between cooperating tasks executed by different computers. The task communicator comprises a data values table (8... | 06/01/1982 |
| 4330845 | Guess-ahead feature for a keyboard-display terminal data input system A guess-ahead feature for an interactive terminal having a keyboard and a display screen where input data is entered via the keyboard and displayed. Means are provided for continually evaluating input data to determine if it is the beginning of a string o... | 05/18/1982 |
| 4330844 | Logic timing system for tape device adapter A hardware logic timing system for a tape device adapter is disclosed for accommodating the exchange of control information and data between a medium performance device controller (MPDC) and mass storage devices. Plural timing frequencies exhibiting selec... | 05/18/1982 |
| 4330825 | Device for automatic control of the storage capacity put to work in data processing systems A device is provided for automatically determining the storage capacity of a data processing or transmission system and signalling when the storage capacity is inadequate to handle an incoming address. The store includes a plurality of storage fractions m... | 05/18/1982 |
| 4328559 | Apparatus for exchange of data between central station and peripheral stations and system for effecting same In a system for an exchange of data between a central station and peripheral stations, the sharing of time in a multiplex channel is effected by the transmission of address signals. For each peripheral station, the address signal consists of a single bina... | 05/04/1982 |
| 4327410 | Processor auto-recovery system A system for preserving data associated with a memory unit having a volatile section and a non-volatile section. The system controls the transfer of data between the volatile and non-volatile sections of the memory unit and also handles successive impendi... | 04/27/1982 |
| 4325118 | Instruction fetch circuitry for computers The invention is used in a computer system to buffer the transfer of program portions from a system having a first bus width to instruction processing logic having a second bus width. An instruction register receives program portions via a system bus from... | 04/13/1982 |
| 4323964 | CPU Employing micro programmable control for use in a data processing system A microprogrammed processor having a versatile hardware and data path configuration in which control signals for data paths, the ALU function, the shifter and all other control signals are derived from the current microprogram control word which is normal... | 04/06/1982 |
| 4323966 | Operations controller for a fault-tolerant multiple computer system An operations controller for each computer in a multiple computer system is disclosed. Each operations controller controls the operations of its associated computer, so that all of the computers cooperate to perform system functions in a fault-tolerant ma... | 04/06/1982 |
| 4323963 | Hardware interpretive mode microprocessor In a data processor system comprising memory means containing subroutines each having low level instructions with the last instruction being an INTERPRET instruction, and high level language instructions which point to the starting addresses of said subro... | 04/06/1982 |
| 4322791 | Error display systems An error display circuit in a data processing device containing an independent processor circuit is set by an initializing signal generated when a power source is turned on and reset by the operation of the processor circuit when the initializing signal i... | 03/30/1982 |
