| Patent No. | Patent Title: |
| 7587580 | Power efficient instruction prefetch mechanism |
| 7464202 | Clock system for controlling autonomous transfer of data |
| 7461243 | Deferred branch history update scheme |
| 7461236 | Transferring data in a parallel processing environment |
| 7454596 | Method and apparatus for partitioned pipelined fetching of multip... |
| 7454594 | Processor for realizing software pipelining with a SIMD arithmeti... |
| 7454602 | Pipeline having bifurcated global branch history buffer for index... |
| 7447881 | Branch prediction apparatus and method |
| 7447882 | Context switching within a data processing system having a branch... |
| 7447885 | Reading prediction outcomes within a branch prediction mechanism |
| 7447873 | Multithreaded SIMD parallel processor with loading of groups of t... |
| 7444498 | Load lookahead prefetch for microprocessors |
| 7441105 | Reducing multiplexer circuitry for operand select logic associate... |
| 7441100 | Processor synchronization in a multi-processor computer system |
| 7437541 | Atomically updating 64 bit fields in the 32 bit AIX kernel |
| 7437537 | Methods and apparatus for predicting unaligned memory access |
| 7437538 | Apparatus and method for reducing execution latency of floating p... |
| 7434028 | Hardware stack having entries with a data portion and associated ... |
| 7434029 | Inter-processor control |
| 7434040 | Copying of unaligned data in a pipelined operation |
| 7434035 | Method and system for processing instructions in grouped and non-... |
| 7430656 | System and method of converting data formats and communicating be... |
| 7430652 | Devices for performing multiple independent hardware acceleration... |
| 7430657 | System, method and device for queuing branch predictions |
| 7428632 | Branch prediction mechanism using a branch cache memory and an ex... |
| 7426629 | Processing activity masking in a data processing system |
| 7421565 | Method and apparatus for indirectly addressed vector load-add -st... |
| 7421568 | Power saving methods and apparatus to selectively enable cache bi... |
| 7421570 | Method for managing a microprocessor stack for saving contextual ... |
| 7421567 | Using a modified value GPR to enhance lookahead prefetch |
| 7421566 | Implementing instruction set architectures with non-contiguous re... |
| 7418577 | Fail instruction to support transactional program execution |
| 7418585 | Symmetric multiprocessor operating system for execution on non-in... |
| 7418584 | Executing system management mode code as virtual machine guest |
| 7415600 | Microprocessor that carries out context switching by shifting con... |
| 7415597 | Processor with dependence mechanism to predict whether a load is ... |
| 7412586 | Switch memory architectures |
| 7412589 | Method to detect a stalled instruction stream and serialize micro... |
| 7412593 | Processor for processing a program with commands including a moth... |
| 7406587 | Method and system for renaming registers in a microprocessor |
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