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| Number | Title | Issue Date |
| 6370495 | Method and apparatus for simulating a storage component The present invention simulates the behavior of a storage component by first determining whether a timing violation has occurred for the storage component. If one or more timing violations is detected, then an x (indicating uncertainty) is reflected at th... | 04/09/2002 |
| 6336088 | Method and apparatus for synchronizing independently executing test lists for design verification Method and apparatus for synchronizing the execution of the two or more test lists at desired synchronization points, while allowing the test lists to execute in a non-deterministic manner between the synchronization points is disclosed. A test driver is ... | 01/01/2002 |
| 6327556 | AT-speed computer model testing methods A computer implemented method for performing testing of a computer model of an integrated circuit design is disclosed. The method includes initially generating a first AVF test file for a first integrated circuit design having slow characteristics. Then, ... | 12/04/2001 |
| 6324493 | Method and apparatus for modeling electromagnetic interactions in electrical circuit metalizations to simulate their electrical characteristics A so-called multipole decomposition is employed for modeling the charge and current distributions and the interactions of those distributions in metalization sub units arising from electrical signals in those metalization sub units. Specifically, a variab... | 11/27/2001 |
| 6324495 | Synchronous parallel system for emulation and discrete event simulation A synchronous parallel system for emulation and discrete event simulation having parallel nodes responds to received messages at each node by generating event objects having individual time stamps, stores only the changes to the state variables of the sim... | 11/27/2001 |
| 6321186 | Method and apparatus for integrated circuit design verification A method for verifying an integrated circuit design using constraint information to develop a weighted data structure. In one embodiment, a binary decision diagram (BDD) includes a plurality of nodes (401, 402, 403, 404, 405, 406, 407, 420, and 430) repre... | 11/20/2001 |
| 6321184 | Reduction of arbitrary L1-L2 circuits for enhanced verification A method of generating a digital circuit model that has fewer latches than the circuit being modeled. Initially, a determination of whether the digital circuit is reducible is made. The digital circuit suitably includes one or more primary inputs, one or ... | 11/20/2001 |
| 6321185 | Estimation system of LSI power consumption Power consumption of an LSI chip is estimated at the beginning stage of the designing without using the HDL description. An I/O part power of a new designing LSI chip is calculated by an equation with using the outside specifications required by the appli... | 11/20/2001 |
| 6311142 | Methods for designing pop-up cards, and cards produced thereby An interactive development environment for design and placement of tiered geometrical objects, such as objects used in pop-up card designs. Relations between objects are represented mathematically, allowing computerized modeling and enforcement of design ... | 10/30/2001 |
| 6298317 | Enhanced functional testing through the filtration of non-subtle mutations A function simulates and verifies a computer program by inserting a syntactic mutation into one of the source code modules comprising the program. The mutated computer program is compiled and subjected to a subtlety check which detects non-subtle (i.e., e... | 10/02/2001 |
| 6295516 | Data transmission apparatus and data transmission system A data transmission apparatus and a data transmission system, and more particularly, a data transmission apparatus which includes a detection unit for detecting a bandwidth of data transmission actually used in a transmission line, a calculation unit for ... | 09/25/2001 |
| 6292765 | Method for automatically searching for functional defects in a description of a circuit A programmed computer searches for functional defects in a description of a circuit undergoing functional verification in the following manner. The programmed computer simulates the functional behavior of the circuit in response to a test vector, automati... | 09/18/2001 |
| 6292766 | Simulation tool input file generator for interface circuitry The present invention is a simulation tool input file generator implemented in a computer system that permits a designer to efficiently and effectively create and modify electrical circuit simulation tool input files. The simulation tool input file genera... | 09/18/2001 |
| 6292763 | Methods for designing variable cycle gas turbine engines A method for designing a variable cycle gas turbine engine having a fan assembly with a maximum air flow there through and a maximum pressure ratio there across during operation at a fan speed and a plurality of variable pitch vanes, which method includes... | 09/18/2001 |
| 6289300 | Integrated circuit with embedded emulator and emulation system for use with such an integrated circuit A data processor is provided with an embedded debugger. The debugging function is provided by the execution of a debugging program which is stored in reserved, non-volatile memory which is internal to the data processor. During the debug mode, the data pr... | 09/11/2001 |
| 6289297 | Method for reconstructing a video frame received from a video source over a communication channel An adaptive region-based, multi-scale, motion compensated video compression algorithm design for transmission over hostile communication channels. The algorithm is embodied in a video encoder that extracts spatial information from video frames to create v... | 09/11/2001 |
| 6278966 | Method and system for emulating web site traffic to identify web site usage patterns A method and device to generate behavior for emulated visitors traversing an internet web site. The visitors may display behavior that is indistinguishable from those of actual users, a subset of the actual users, or the behavior may be purely hypothetica... | 08/21/2001 |
| 6272449 | Computer system and process for explaining behavior of a model that maps input data to output data The present invention provides a description of the behavior of a model that indicates the sensitivity of the model in subspaces of the input space and which indicates which dimensions of the input data are salient in subspaces of the input space. By impl... | 08/07/2001 |
| 6272447 | Fabrication and design of structural members A method of designing structural members for a building frame using a computer includes the steps of inputting a predetermined plan of the layout and orientation of the structural members. This information is then stored. The computer then analyses the st... | 08/07/2001 |
| 6266629 | Large signal model for a pseudomorphic heterojunction electron mobility transistor A method is provided for large signal modeling of a field effect transistor. The method includes establishing a small signal model for the transistor, such model having a gate-source capacitance Cgs and a drain-gate capacitance Cdg, ... | 07/24/2001 |
| 6263301 | Method and apparatus for storing and viewing data generated from a computer simulation of an integrated circuit A method and apparatus for managing simulation results involves identifying distinct transactions in a group of simulation results so that the simulation results can be stored and viewed on a transaction basis instead of as a single continuous block of si... | 07/17/2001 |
| 6246974 | Method of determining characteristics of a rotary drag-type drill bit A method of determining characteristics of a rotary drag-type drill bit comprises the steps of: creating a computerized representation of the cutters on the drill bit, and then, with each cutter in turn, projecting the shape of the cutter onto a fixed pla... | 06/12/2001 |
| 6246975 | Computer architecture and process of patient generation, evolution, and simulation for computer based testing system A computer implemented simulation and evaluation method simulates interventions to a patient by a user, and evaluates the interventions responsive to predetermined criteria and the interventions. The method includes defining a test area to evaluate the us... | 06/12/2001 |
| 6243665 | Monitoring and control apparatus incorporating run-time fault detection by boundary scan logic testing The monitoring control apparatus according to the present invention performs a test on each integrated circuit that supports the boundary scan test method loaded on CPU board 4 and control board 5, and on the connection relationships of these integrated c... | 06/05/2001 |
| 6243668 | Instruction set interpreter which uses a register stack to efficiently map an application register state A method of executing a program compiled for a base instruction set architecture different than a native instruction set architecture, on a native machine by organizing a runtime system module into at least a low level domain, a medium level domain, and a... | 06/05/2001 |
| 6240377 | Integrated circuit with embedded reprogrammable EEPROM and emulation method to facilitate debugging An E2 PROM controller is provided for an emulation chip. An E2 PROM is connected to a CPU via a memory interconnect bus. The E2 PROM and the CPU are also connected to each other via a peripheral circuit interconnect bus in... | 05/29/2001 |
| 6240376 | Method and apparatus for gate-level simulation of synthesized register transfer level designs with source-level debugging Methods of instrumenting synthesizable source code to enable debugging support akin to high-level language programming environments for gate-level simulation are provided. One method of facilitating gate level simulation includes generating cross-referenc... | 05/29/2001 |
| 6240375 | Method of simulating an integrated circuit for error correction in a configuration model, and a computer-readable recording medium The number (Nc) of conductor regions and the number (Ncell(i)) of cells constituting each conductor region (ci) are calculated from the result of a configuration simulation. Each conductor region (ci) is judged whether or not the number (Ncell(i)) of cell... | 05/29/2001 |
| 6233540 | Design environment and a method for generating an implementable description of a digital system The present invention is a design apparatus compiled on a computer environment for generating from a behavioral description of a system comprising at least one digital system part, an implementable description for said system, said behavioral description ... | 05/15/2001 |
| 6230112 | Pneumatic tire designing method When a single performance or a plurality of antinomical performances are to be obtained, the best mode of a tire is designed under a given condition. A basic shape model using one block as a reference shape is obtained (100). An object function representi... | 05/08/2001 |
| 6230119 | Integrated circuit with embedded emulator and emulation system for use with such an integrated circuit A data processor is provided in which an embedded emulator communicates with a control emulation system using a serial communications link involving one pin of the data processor package.... | 05/08/2001 |
| 6223145 | Interactive interface for specifying searches An interactive interface for creating a search query for a corpus of machine-readable documents, each of which is associated with at least one category of a category hierarchy. The interactive interface includes a cone tree generation component, a query s... | 04/24/2001 |
| 6219628 | System and method for configuring an instrument to perform measurement functions utilizing conversion of graphical programs into hardware implementations A system and method for configuring an instrument to perform measurement functions, wherein the instrument includes a programmable hardware element. A graphical program is first created, wherein the graphical program implements a measurement function. The... | 04/17/2001 |
| 6208953 | Method for monitoring plants with mechanical components In a method for monitoring plants with mechanical components, measured values (xiT ; xiu) are determined at predeterminable time intervals for a fixed set of parameters (xi). The measured values (xiT) which are ... | 03/27/2001 |
| 6205413 | End-user oriented performance monitoring system for interactive end-to-end data communications Performance monitoring of network connections is an integral and necessary part of network operation, administration and management. The performance monitoring reflects the "goodness" of the communication system in supporting "high-level" data communicati... | 03/20/2001 |
| 6202041 | Electrical power network modelling method A versatile modelling for any standard power system component is disclosed, by which the component modules can be easily plugged into the network module to form a small perturbation state space model of the entire system irrespective of the complexity of ... | 03/13/2001 |
| 6202044 | Concurrent hardware-software co-simulation A digital logic simulation/emulation system (20) operates in an engaged operating mode in which a digital-logic simulation process (22) transmits stimulation-control data to a hardware pod (32) for controlling stimulation of a digital logic circuit. In re... | 03/13/2001 |
| 6199031 | HDL simulation interface for testing and verifying an ASIC model An interface system for testing and verifying the design of an ASIC at different levels of abstraction, wherein the ASIC includes a logic entity and a processor entity. The system of the present invention is embodied as software which executes within a co... | 03/06/2001 |
| 6199030 | Heightened realism for computer-controlled units in real-time activity simulation Enhanced realism of a real-time simulator having multiple computer-controlled units results from making the units capable of reacting to only those other units that each of them can be aware of because of their spatial relationships to the unit. Awareness... | 03/06/2001 |
| 6199029 | Topography simulation method and system of plasma-assisted etching process A topography simulation method using the Monte Carlo method is provided, which simulates the post-etching topography of a plasma-assisted etching process affected by different etching species such as the ion-assisted etching process. (a) A bulk- and/or sh... | 03/06/2001 |
