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| Number | Title | Issue Date |
| 6531897 | Global clock self-timed circuit with self-terminating precharge for high frequency applications A global clock self-timed circuit initiates a precharge pulse in response to which a domino node is precharged. A self-terminating precharge circuit coupled to the global clock self-timed circuit and the domino node terminates the precharge pulse after th... | 03/11/2003 |
| 6515510 | Programmable logic array with vertical transistors A programmable logic array is provided. The programmable logic array includes first and second logic planes. The first logic plane receives a number of input signals. The first logic plane includes a plurality of vertical transistors arranged in rows and ... | 02/04/2003 |
| 6486755 | Vertical transition device for differential stripline paths and optical module A vertical transition device for differential stripline paths, connects differential microstrip paths on a horizontal plane with differential triplate paths on another horizontal plane in a multilayered architecture. The differential microstrip paths incl... | 11/26/2002 |
| 6486703 | Programmable logic array with vertical transistors A programmable logic array is provided. The programmable logic array includes first and second logic planes. The first logic plane receives a number of input signals. The first logic plane includes a plurality of vertical transistors arranged in rows and ... | 11/26/2002 |
| 6483341 | CMOS-microprocessor chip and package anti-resonance apparatus An apparatus for regulating resonance in a micro-chip has been developed. The method includes connecting a de-coupled capacitance across the supply and ground voltages, and connecting a band-pass shunt regulator that is in parallel to the capacitor across... | 11/19/2002 |
| 6483349 | Semiconductor integrated circuit device Differential amplifier circuits that receive input signals fed through external terminals are served with a first operation voltage and a second operation voltage through a first switching MOSFET and a second switching MOSFET, said first and second switch... | 11/19/2002 |
| 6480024 | Circuit configuration for programming a delay in a signal path A circuit configuration includes two signal path sections that are used to program the delay of a signal path, in particular in DRAMs. The two signal path sections have different delays and can be driven in parallel at the input end. The two signal path s... | 11/12/2002 |
| 6480020 | Printed circuit assembly having integrated resistors for terminating data and control lines of a host-peripheral interface A printed circuit board assembly (PCBA) includes first and second integrated-circuit terminals and first and second connector terminals. A first transmission line transmits a data signal and a second transmission line transmits a clocking signal. The PCBA... | 11/12/2002 |
| 6480027 | Driver circuitry for programmable logic devices Driver circuitry for programmable logic devices may include a module comprising a driver and associated hardware-programmable input and/or output routing connection. Instances of the generalized driver module may be included anywhere on the programmable l... | 11/12/2002 |
| 6476638 | Input driver circuit with adjustable trip point for multiple input voltage standards An input driver circuit for accommodating a plurality of input/output voltage standards is provided. The input driver circuit employs an adjustable trip point that can be calibrated for multiple input voltage standards. The adjustable trip point is provid... | 11/05/2002 |
| 6472902 | Semiconductor device A semiconductor device is provided having an internal circuit in which input data is gated and supplied to the internal circuit according to an internal control signal generated within the semiconductor device. The semiconductor device has N number (N bei... | 10/29/2002 |
| 6452418 | Level shifter with independent grounds and improved EME-isolation A driving circuit provides a symmetric differential driving signal relative to one set of voltage potentials to a driver circuit that drives an output node to another set of voltage potentials. The differential driving signals from the driving system are ... | 09/17/2002 |
| 6433580 | Architecture and interconnect scheme for programmable logic circuits An architecture and distributed hierarchical interconnect scheme for field programmable gate arrays (FPGAs). The FPGA is comprised of a number of cells which perform logical functions on input signals. Programmable intraconnections provide connectability ... | 08/13/2002 |
| 6429684 | Circuit having dynamic threshold voltage A body-tied-to-drain transistor having significantly reduced gate delay and being particularly appropriate for large drivers where a series of inverters is used. The basic configuration ties the drain of the transistor to the body of the transistor when t... | 08/06/2002 |
| 6404233 | Method and apparatus for logic circuit transition detection The present invention discloses an apparatus and method for determining the speed of a logic circuit relative to the clock. The preferred embodiment utilizes dynamic logic to deliver a critical signal to a transition detection circuit, which performs the ... | 06/11/2002 |
| 6396168 | Programmable logic arrays A programmable logic array (PLA) includes at least one AND plane including an array of transistors arranged in rows and columns. The transistors belonging to a same column may be connected in series with each other. Two end conduction terminals of the ser... | 05/28/2002 |
| 6396304 | Programmable logic array integrated circuits with blocks of logic regions grouped into super-blocks A programmable logic array integrated circuit device has logic regions grouped in blocks, which are in turn grouped in super-blocks. The super-blocks are disposed on the device in a two-dimensional array of intersecting rows and columns. Global conductors... | 05/28/2002 |
| 6392437 | Programmable multi-standard I/O architecture for FPGAs The invention discloses an architecture for the input/output buffer section of an FPGA. It provides a convenient and efficient addressing scheme for addressing fuse matrices that are used to configure programmable input/output buffers in the FPGA. The pro... | 05/21/2002 |
| 6388470 | High voltage CMOS signal driver with minimum power dissipation The system and method facilitates the transmission of relatively high voltage signals via a thin oxide gate CMOS device without an excessively detrimental electric field build up across the thin oxide layers forming a gate in a CMOS device. The high volta... | 05/14/2002 |
| 6388463 | Circuit arrangement for bias adjustment of bus levels In a system for the transmission of logic levels via a bus the recessive level, being of higher impedance in comparison with the dominant level, is not adjusted by means of a resistor but by means of a termination arrangement with three break points in th... | 05/14/2002 |
| 6388469 | Multiple power supply output driver An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a first control signal and a second control signal in response to (i) a first input signal, (ii) a second input signal and (iii) a voltage contro... | 05/14/2002 |
| 6384631 | Voltage level shifter with high impedance tri-state output and method of operation There is disclosed a voltage level shifter that receives an input signal having a maximum Logic 1 value of VDD and produces an output signal having a maximum Logic 1 value of VDDI/O, where VDDI/O is greater than VDD. The voltage level shifter comprises: 1... | 05/07/2002 |
| 6380760 | Integrated circuit for handling buffer contention and method thereof In one embodiment, an integrated circuit (10, 110) has a contention detection circuit (12, 112) coupled to a tri-stateable output buffer (18, 118). The contention detection circuit (12, 112) provides a contention tri-state control signal (34, 134) to the ... | 04/30/2002 |
| 6377073 | Structure and method for reduction of power consumption in integrated circuit logic A reduced power dissipation integrated circuit. Power dissipation within a CMOS circuit is reduced by substitution of multi-level buses with several thresholds for binary state buses with a single threshold. A significant portion of an IC's power dissipat... | 04/23/2002 |
| 6373280 | Fast signal conductor networks for programmable logic devices A programmable logic integrated circuit device has a plurality of areas of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such areas. A so-called "fast conductor" network is provided on the device ... | 04/16/2002 |
| 6373277 | Line driver having variable impedance termination A line driver having variable impedance termination includes an impedance, a 1st variable feedback, a 2nd variable feedback, a summing module and a gain module. The 1st and 2nd variable feedbacks provide feedbac... | 04/16/2002 |
| 6369608 | Conditioning semiconductor-on-insulator transistors for programmable logic devices Method and apparatus for preconditioning and in-use conditioning of transistors formed on a semiconductor-on-insulator structure is described. More particularly, transistors of a programmable logic device (PLD), such as a field programmable gate array (FP... | 04/09/2002 |
| 6366132 | Soft error resistant circuits In some embodiments, the invention includes a soft error resistant latch circuit. The latch circuit includes a storage node, a feedback node, and an inverter between the storage node and the feedback node. The latch circuit also includes split connection ... | 04/02/2002 |
| 6366134 | CMOS dynamic logic circuitry using quantum mechanical tunneling structures CMOS semiconductor dynamic logic (300) is disclosed, comprising dynamic logic circuitry (302) and tunneling structure circuitry (328) coupled to the dynamic logic circuitry; where the tunneling structure circuitry is adapted to hold a node (308) voltage s... | 04/02/2002 |
| 6366119 | Programmable logic device macrocell with improved logic capability A macrocell for a programmable logic device includes circuitry for allowing a neighboring macrocell to borrow various numbers of the product terms of the macrocell. The macrocell can continue to make full use of its product terms that are not thus borrowe... | 04/02/2002 |
| 6366114 | Output buffer with control circuitry Techniques and circuitry are used to reduce noise at the output (136) of an integrated circuit. The control circuit of the output buffer may reduce ground or power noise, or both. The control circuitry includes a ramp control circuit (153, 163) and di/dt ... | 04/02/2002 |
| 6366125 | Digital output circuit A digital signal output circuit is provided. The digital signal output circuit includes capacitor forming means connected as an integrator, charging means, discharging means, means for selectively coupling, and a digital signal output. The charging means ... | 04/02/2002 |
| 6366133 | Logic circuit A wordline driver has enable circuitry optimized for positive-going input transitions and disable circuitry optimized for transitions in a disable input which would cause the output to become disabled. The optimization is achieved by suitably dimensioning... | 04/02/2002 |
| 6362652 | High voltage buffer for submicron CMOS An input circuit allows input buffers fabricated using submicron CMOS technologies to receive input signals having a voltage swing of 5V. The input circuit uses a cascode transistor to bias the drain of the input transistor so that the VGD of t... | 03/26/2002 |
| 6362653 | High voltage tolerant receivers A high voltage tolerant receiver that matches a voltage drop across an NFET pass-gate at the input to the receiver with a voltage drop across a semiconductor device, formatted as a diode, and connected between an input stage and an input stage voltage sup... | 03/26/2002 |
| 6362657 | Small aperture latch for use with a differential clock A latch having a pass gate, multiple clock paths connected to the pass gate, and a data path connected to the pass gate, wherein the data path and the multiple clock paths have the same number and types of elements.... | 03/26/2002 |
| 6362659 | Domino logic family A domino logic circuit and circuit family is disclosed that has reduced the capacitance on the evaluation node for increased performance. The domino logic circuit preferably includes an inverter, a pre-charge transistor, a logic block, and a pre-charge co... | 03/26/2002 |
| 6362654 | Bidirectional repeater using high and low threshold detection A repeater employs multiple threshold detectors to distinguish between signals from external devices and signals generated within the repeater. Signals that are sent from the repeater are configured to be between two threshold levels, so that a detector a... | 03/26/2002 |
| 6359463 | Method and apparatus for reducing induced switching transients An attenuating circuit for reducing the inductively induced voltage transients in an electrical signal. The attenuating circuit is formed by a primary circuit and a smoothing circuit both coupled to a voltage source through an inductive conductor. The pri... | 03/19/2002 |
| 6359462 | Method and apparatus for reducing induced switching transients An attenuating circuit for reducing the inductively induced voltage transients in an electrical signal. The attenuating circuit is formed by a primary circuit and a smoothing circuit both coupled to a voltage source through an inductive conductor. The pri... | 03/19/2002 |
