Did You Know...
...that several people are credited with the invention of the flush toilet? Most people have heard of Thomas Crapper (1837-1910), the sanitary engineer who invented the valve-and-siphon arrangement that made the modern toilet possible. Another claimant to "the throne" was British inventor Alexander Cumming who patented a toilet in 1775. Then there's a nameless Minoan (a native of ancient Crete) who lived 4,000 years ago who supposedly was ahead of his time and created the first flush toilet!
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| Number | Title | Issue Date |
| 6181075 | Power supply circuit for gas discharge tube A power supply for high voltage, low current gas discharge tubes such as neon, argon, and mercury vapor. A free running, flyback oscillator, converts D.C. voltage energy into radio frequency energy by means of a compact, ferrite transformer and associated... | 01/30/2001 |
| 5384728 | Optical information storage apparatus using optical fiber An optical information storage apparatus includes an optical switch element and an optical fiber. The optical switch element receives an optical input and outputs an optical output only when the optical input is equal to or greater than a predetermined va... | 01/24/1995 |
| 5381370 | Memory with minimized redundancy access delay A memory is described that includes a main memory array having a plurality of main memory locations and a redundant memory array having a plurality of redundant memory locations. A main decoding circuit is coupled to the main memory array for decoding an ... | 01/10/1995 |
| 5379146 | Electrochromic pane The present invention has as its subject an electrochromic pane including two glass sheets (1, 2), each coated with a transparent electrically conducting film (3, 4) and separated by an electrode of electrochromic material (5), an electrolyte (6) and a co... | 01/03/1995 |
| 5377140 | Cell for random access memory The memory ratio is improved and the data holding ability on reading data is enhanced by providing a resistive element between an access transistor and a flip-flop, which form a memory cell of a static memory. Even if the threshold voltage of the access t... | 12/27/1994 |
| 5375088 | Random access memory with plurality of amplifier groups A semiconductor memory device operable for reading and writing in a normal mode and in a test mode is divided into memory cell sections each having blocks of memory cells. Data bus lines are connected to the respective blocks, and switches interconnect da... | 12/20/1994 |
| 5375090 | Semiconductor memory device A semiconductor memory device of the present invention includes a plurality of blocks. Each of the blocks includes: a memory cell group including redundancy cells; a memory cell group selection decoder for, in response to an address signal indicative of a... | 12/20/1994 |
| 5367482 | High voltage random-access memory cell incorporation level shifter A level-shifting static random access memory cell includes a first stage having a first P-Channel MOS transistor having its source connected to a high voltage supply rail, and its drain connected to the drain of a first N-Channel MOS transistor. The sourc... | 11/22/1994 |
| 5365483 | Random access memory architecture including primary and signal bit lines and coupling means therefor A differential latching inverter uses a pair of cross-coupled inverters having a skewed voltage transfer function to rapidly sense a differential signal on a pair of bit lines in a random access memory and provide high speed sensing during a read operatio... | 11/15/1994 |
| 5365484 | Independent array grounds for flash EEPROM array with paged erase architechture An improved architecture for an array of flash EEPROM cells with paged erase is provided. The array is formed of a plurality of half-sectors. In each sector, the sources of the memory cell transistors are connected to a separate individual ground line. A ... | 11/15/1994 |
| 5329480 | Nonvolatile random access memory A nonvolatile magnetic random access memory can be achieved by an array of magnet-Hall effect (M-H) elements. The storage function is realized with a rectangular thin-film ferromagnetic material having an in-plane, uniaxial anisotropy and inplane bipolar ... | 07/12/1994 |
| 5321665 | Dual-port memory having a serial register accessing arrangement with pulsed decoding A data processing system includes a video random access memory with a serial register having a serial register tap addressing arrangement wherein tap addresses are decoded from column address factors and are applied to data gates associated stages of the ... | 06/14/1994 |
| 5321549 | Cleaning apparatus for an object lens A cleaning apparatus for an object lens which can provide a sufficient cleaning effect without affecting the supporting mechanism of an objective lens. The cleaning apparatus is inserted into a disk loading portion and cleans the object lens incorporated ... | 06/14/1994 |
| 5319607 | Semiconductor unit The present invention relates to a semiconductor unit including a delay circuit used for an address transition detecting circuit in a storage, wherein a change of an address is detected and, accordingly, an access address in a memory cell is altered. The ... | 06/07/1994 |
| 5317535 | Gate/source disturb protection for sixteen-bit flash EEPROM memory arrays In a flash EEPROM memory array in which a plurality of floating gate field effect transistor memory devices are arranged in rows and columns, in which wordlines are utilized to select rows of such devices and bitlines are utilized to select columns of suc... | 05/31/1994 |
| 5315544 | Radiation-hardened memory storage device for space applications A radiation-hard dynamic random access memory (DRAM) device having reduced sensitivity to single event upset and latchup. The radiation-hard DRAM device includes a high-density configuration of transistors that have undergone neutron bombardment. The high... | 05/24/1994 |
| 5315552 | Memory module, method for control thereof and method for setting fault bit table for use therewith A memory module implementing a desired memory capacity by use of a plurality of memory chips. The memory module has a fault bit substituting device that compensates for fault bits detected in any of the memory chips. This improves the yield of the memory ... | 05/24/1994 |
| 5315545 | High-voltage five-transistor static random access memory cell According to a first aspect of the present invention, a static random access memory cell according to the present invention includes two stages. The first stage has a first P-Channel MOS transistor with its source connected to a high-voltage supply rail, ... | 05/24/1994 |
| 5313434 | Semiconductor memory device A semiconductor memory device having a plurality of memory cells disposed in the form of a matrix with column switch circuits and an address transition detecting circuit. The column switch circuits are each provided for each of said bit line pairs with th... | 05/17/1994 |
| 5311472 | Redundant decoder circuit A redundant decoder circuit includes a restoration circuit for restoring a decoder which activates a redundant memory cell. When the redundant memory cell which should store a predetermined information is disabled, the restoration circuit stops the decode... | 05/10/1994 |
| 5309395 | Synchronous static random access memory Maximum operating speed is achieved in an array of memory cells by performing both read and write operations within a single memory cycle. As outgoing data are read from the memory cells, incoming data are stored immediately in those cells. Once data are ... | 05/03/1994 |
| 5309399 | Semiconductor memory A semiconductor memory has a first internal circuit operated by an external source, a second internal circuit operated by an internal source which outputs an internal voltage lower than that of the external source and a voltage-down-converter supplying th... | 05/03/1994 |
| 5307324 | Semiconductor memory device including address transition detecting circuit A transistor is provided for taking written data between a data bus line and a latch circuit in a main amplifier circuit. The gate of the transistor is supplied with a write control signal generated by a write control circuit in writing operation.... | 04/26/1994 |
| 5307316 | Semiconductor memory unit having redundant structure A semiconductor memory device has a plurality of main memory blocks formed on a chip and each having a redundancy, a sub-memory block formed on the chip and having a substantially identical construction as that of each main memory block, a defect address ... | 04/26/1994 |
| 5305281 | Multiple array memory device with staggered read/write for high speed data access A multiple array memory device formed on a single IC chip performing transfers of a series of data between the device and its interface at high speed. The device includes a memory having a plurality of groups of memory arrays. In a read operation, the dev... | 04/19/1994 |
| 5303182 | Nonvolatile semiconductor memory utilizing a ferroelectric film Two memory cells are formed adjacent each other on a semiconductor substrate. In each memory cell, eight MOS transistors are formed between two selection transistors such that the MOS transistors and the selection transistors are connected in series, and ... | 04/12/1994 |
| 5299169 | Multiport memory device comprising random access port and serial access port A dual port memory device capable of random access and serial access, having a random data input/output port arranged along a power supply wiring formed along one direction with respect to a power supply terminal, and a serial data input/output port arran... | 03/29/1994 |
| 5297076 | Spectral hole burning data storage system and method Phase modulation is used to record data in a spectral hole burning material. A laser and a phase modulator are used to generate both a reference pulse and a phase modulated data pulse to the material. The data is recorded as spectral holes in the absorpti... | 03/22/1994 |
| 5297081 | Electrical erasable programmable read-only memory array A memory (1) operative in an erase mode, a program mode, or a read mode includes a memory cell array, word lines (30, 40, 50, 60), a row decoder (9) connected to the word lines, bit lines (2, 4, 6, 8), a precharge circuit (70, 72, 74, 76, 78, 80) connecte... | 03/22/1994 |
| 5297105 | Semiconductor memory circuit A semiconductor memory circuit selects one memory cell group in response to an address signal having block selection information, first and second significant bit information. First to third memory cell blocks respectively have memory cell groups each inc... | 03/22/1994 |
| 5295114 | Semiconductor memory device with redundant circuit for rescuing from rejection due to large current consumption A semiconductor memory device has regular memory cells arranged in rows and columns, and at least one of the rows is replaced with redundant memory cells when one of the regular memory cells in the row is defective, wherein a fuse element is broken for is... | 03/15/1994 |
| 5295102 | Semiconductor memory with improved redundant sense amplifier control An integrated circuit memory is disclosed which has its primary memory array arranged into blocks and which has redundant columns, each of which can replace a column in any one of the blocks. The redundant columns are selected by way of a redundant column... | 03/15/1994 |
| 5293562 | Device with multiplexed and non-multiplexed address and data I/O capability An electronic device receives data from an EEPROM by sending address information to it on one set of leads and receiving data back from it through a different set of multiplexed address/data leads. The electronic device also sends and receives data to and... | 03/08/1994 |
| 5293564 | Address match scheme for DRAM redundancy scheme An address match scheme is disclosed which allows the alternate selection of fuses blown based on either logic ones or logic zeros in an address.... | 03/08/1994 |
| 5291456 | Data storage control device A data storage control device including a DRAM and a storage device has an address bus common to the DRAM and the storage device, and a control device for selectively applying an address signal relating to the DRAM and another address signal relating to t... | 03/01/1994 |
| 5287318 | Semiconductor memory In a flash-type electrically erasable programmable read-only memory (EEPROM), the erasure block decoder provided in the row decoder outputs a signal for simultaneously driving half the erasure line drivers in the erasure line driver array, or a signal for... | 02/15/1994 |
| 5283759 | One-time-programmable EEPROM cell The invention relates to a one-time-programmable read-only memory cell, abbreviated as PROM. According to the prior art, PROM cells are programmed by the deliberate destruction of a component. Since the information is burnt into the memory cell in this wa... | 02/01/1994 |
| 5282169 | Compensated sense circuit for storage devices The sense circuit recognizes the virgin or programmed status of cells in storage devices (e.g. non-volatile memories of the type with unbalanced loads), and includes a sense amplifier (SA) having a first input (Y) connected to a number of selectable virgi... | 01/25/1994 |
| 5280449 | Data memory and method of reading a data memory A data memory and a method of reading a data memory are described. Data words (Word0, Word1, Word2, Word3) are stored within the data memory within an array of memory cells arranged in columns and rows. A particular data word within a memory cell is acces... | 01/18/1994 |
| 5278794 | NAND-cell type electrically erasable and programmable read-only memory with redundancy circuit A NAND-cell type electrically erasable and programmable read only memory includes an array of rows and columns of memory cells associated with parallel bit lines on a semiconductive substrate. Each memory cell essentially consists of a floating-gate field... | 01/11/1994 |
