| Patent No. | Patent Title: |
| 5842001 | Clock signal adjusting method and apparatus |
| 5774727 | Parallel processing system for virtual processor implementation o... |
| 5729719 | Synchronization circuit for clocked signals of similar frequencie... |
| 5687314 | Method and apparatus for assisting data bus transfer protocol |
| 5666535 | Microprocessor and data flow microprocessor having vector operati... |
| 5664164 | Synchronization of one or more data streams |
| 5655112 | Method and apparatus for enabling data paths on a remote bus |
| 5649174 | Microprocessor with instruction-cycle versus clock-frequency mode... |
| 5649201 | Program analyzer to specify a start position of a function in a s... |
| 5644760 | Printed circuit board processor card for upgrading a processor-ba... |
| 5642508 | Distributed control method and apparatus for job execution |
| 5630111 | Processing and playback apparatus for recorded digital data |
| 5627540 | Remote control system having full-function and abbreviated-functi... |
| 5625805 | Clock architecture for synchronous system bus which regulates and... |
| 5625822 | Using sorting to do matchup in smart recompilation |
| 5619702 | Method and apparatus for programming registers using simplified c... |
| 5615241 | Programmable rate generator |
| 5615358 | Time skewing arrangement for operating memory in synchronism with... |
| 5613122 | Object-oriented operating system |
| 5613125 | Method and system for selectively defining hardware parameters in... |
| 5608897 | Programmable linear feedback shift register timeout mechanism |
| 5603016 | Method for synchronizing playback of an audio track to a video tr... |
| 5598555 | Data transmission apparatus |
| 5598556 | Conditional wait state generator circuit |
| 5594903 | Operating System architecture with reserved memory space resident... |
| 5594893 | System for monitoring and controlling operation of multiple proce... |
| 5592659 | Timing signal generator |
| 5590316 | Clock doubler and smooth transfer circuit |
| 5588144 | Storage system having a bus common to a plurality of kinds of gro... |
| 5579482 | Method and apparatus for storing interface information in a compu... |
| 5579522 | Dynamic non-volatile memory update in a computer system |
| 5579520 | System and methods for optimizing compiled code according to code... |
| 5572720 | Method of extending capacity of a microprocessor timer |
| 5572718 | Mechanism for dynamically determining and distributing computer s... |
| 5572731 | Sequentially navigated object oriented computer system |
| 5572721 | High speed serial interface between image enhancement logic and r... |
| 5572723 | Dynamic clock mode indicator |
| 5561801 | System and method for multilevel promotion |
| 5560001 | Method of operating a processor at a reduced speed |
| 5560002 | Method of testing a microprocessor by masking of an internal cloc... |
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