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| Number | Title | Issue Date |
| 5404542 | Power line switching circuit with monitor A power line coupling and decoupling circuit for furthering peripheral system reliability. The circuit is used in a computer system which includes a host computer attached to a peripheral system via a SCSI communication interface. A light emitting diode i... | 04/04/1995 |
| 5377331 | Converting a central arbiter to a slave arbiter for interconnected systems A method and apparatus are disclosed for allowing at least one computer subsystem, having a central arbiter, to be interconnected with a host system also including a central arbiter. Conversion logic is added to each computer subsystem desired to be inter... | 12/27/1994 |
| 5377334 | Fast asynchronous resource master-slave combination Resource master and slave combinations operating from separate local clocks asynchronously even though there may be wide speed variations among the devices, eliminating the need to synchronize the trailing edges of generated control signals with the local... | 12/27/1994 |
| 5363487 | Method and system for dynamic volume tracking in an installable file system A method and apparatus interfaces a computer operating system with a storage volume, which is all or part of a data storage media such as a removable floppy-type disk or a hard disk. In a preferred embodiment, the method and apparatus select and associate... | 11/08/1994 |
| 5361364 | Peripheral equipment control device A peripheral equipment control LSI interposed between an SCSI bus connected to a main CPU and peripheral equipment such as a file device. The LSI is divided into two major blocks. One block recognizes an SCSI protocol ID signal sent over the SCSI bus. The... | 11/01/1994 |
| 5355499 | Interruption circuit operable at a high speed In an interruption circuit, each of a multiplicity of interruption generating units (12) is for generating an interruption signal upon occurrence of an interruption request. A scanning arrangement scans the units to specify one of them at a time as a part... | 10/11/1994 |
| 5353235 | Wire length minimization in channel compactor A method of routing interconnections of devices in a planar field by the use of a computer. The method effectively shortens the length of all interconnections, including interconnections which connect points on the same device, in accordance with design r... | 10/04/1994 |
| 5349668 | Battery operated computer having improved battery monitor and cell reversal protection circuit A battery operated computer includes a battery having a plurality of serially connected banks of battery cells that are monitored during operation of the computer to detect a nearly depleted battery bank and a fully depleted battery bank. The computer als... | 09/20/1994 |
| 5339394 | I/O register protection circuit A data processing system is provided that includes a plurality of processors each including a circuit for providing a busy signal. The system also includes a plurality of registers for storing data wherein each register is dedicated to a selected processo... | 08/16/1994 |
| 5339443 | Arbitrating multiprocessor accesses to shared resources In a multiprocessor computer system, an access request and an access grant register is provided for storing an access request and an access grant semaphore for each shared resource. The access request and grant semaphores having a number of access request... | 08/16/1994 |
| 5339448 | Microprocessor with improved internal transmission A microprocessor according to the present invention comprises a sub-read bus, to which output terminals of registers of a register file of the microprocessor are coupled. The sub-read bus is in turn coupled to a main read bus of the microprocessor through... | 08/16/1994 |
| 5337413 | Environment monitoring system for standard interface bus computer systems An apparatus and method for monitoring the environment of remote components attached to a host processor by means of a standard interface bus having a limited number of address ports. The invention includes a host adapter incorporating a standard bus repe... | 08/09/1994 |
| 5333279 | Self-timed mesh routing chip with data broadcasting A method and apparatus providing for data broadcasting in a two dimensional mesh of processor nodes is disclosed. In accordance with the present invention, a self-timed message routing chip is coupled to each processor node, thereby forming a two dimensio... | 07/26/1994 |
| 5333277 | Data buss interface and expansion system A Buss Interface and Expansion System, which attaches to a SCSI buss provides, means for increasing the number of devices which can be attached to the buss, provides means for data compressing and decompressing data, and means for use by a host computer a... | 07/26/1994 |
| 5329621 | Microprocessor which optimizes bus utilization based upon bus speed A data processing apparatus having a bus speed counter for determining the bus speed of a previous bus cycle. This previous bus speed information is then used to optimize bus utilization. This bus speed information is particularly useful for determining w... | 07/12/1994 |
| 5327565 | Data processing apparatus A macroservice engine is provided to exclusively carry out a sequence control in a processing of a macroservice. On the other hand, a command execution unit carries out no macroservice, but generates a bus cycle exciting request for a bus control unit, wh... | 07/05/1994 |
| 5327538 | Method of utilizing common buses in a multiprocessor system In a multiprocessor system wherein a main storage is divided into a plurality of banks and a plurality of common buses are provided, in order to access the main storage. Each processor selects and acquires one of the buses in accordance with the utilizati... | 07/05/1994 |
| 5327540 | Method and apparatus for decoding bus master arbitration levels to optimize memory transfers A buffer management scheme for optimally configuring a data buffer within a computer system which includes a plurality of bus masters connected through a Micro Channel bus and the data buffer to a shared resource, such as memory. The scheme decodes unique... | 07/05/1994 |
| 5327539 | Access processing system in information processor In an access processing system in an information processor, the information processor includes: an access device (10, 11) for generating an access request signal; an accessed device (13) provided with a memory means (30) that is accessed by the access dev... | 07/05/1994 |
| 5325491 | Method and apparatus for extending a computer bus Disclosed is a bus expansion unit for extending the bus of a computer system which has an asynchronous bus cycle. The bus expansion unit includes an asynchronous state machine which uses a delay line to determine some of its states. The bus expansion unit... | 06/28/1994 |
| 5323403 | Method and apparatus for maximizing process throughput Two identical CRC circuits are cross coupled to make alternate CRC calculations based on the other CRC circuit's calculation. Throughput of the CRC code calculation is improved by applying alternate input data simultaneously at each of the CRC circuits so... | 06/21/1994 |
| 5321606 | Data transforming method using externally provided transformation rules In transformation from a symbol string to a term, transformation rules received describe structures of input symbol strings in the form of a context-free grammar, and include structures of output terms as arguments of terminal symbols and non-terminal sym... | 06/14/1994 |
| 5321818 | System for arbitrating for access on VME bus structures System for providing self-selection arbitration among a plurality of slave processors connected to a VME back plane. The slave processors are connected to a common ID bus, interrupt line, and acknowledge bus. Slave processors contend for access to the VME... | 06/14/1994 |
| 5317751 | Method and apparatus for placing a trainline monitor system in a layup mode A method for placing a multi-car train with a communication network in an energy saving layup mode, the communication network having a master node interconnected to at least one other node via a train bus, the train having a head car for carrying the mast... | 05/31/1994 |
| 5313642 | Power interface for peripheral devices An interface (12) is disclosed for coupling a peripheral device (18) to the serial port (14) of a computer (16). In one application, the interface allows the serial port to provide the power required by a scanner for operation. To reduce power consumption... | 05/17/1994 |
| 5313601 | Request control apparatus A controller for controlling requests to memory, said requests involving executing in a computer system an instruction having a variable length operand, for use in a computer system for managing the main store in a page size of 2m byte units by... | 05/17/1994 |
| 5313626 | Disk drive array with efficient background rebuilding A disk drive array with a controller which provides: dynamic remapping for grown defects in the disk drives, multi-thread request processing with a variable number of forkings, defect tracking with both logical and physical lists, guarded writes of less t... | 05/17/1994 |
| 5307462 | Switch for sharing a peripheral device Disclosed is a switch that allows a peripheral device, such as a printer, to be shared by multiple computer systems. The switch connects to each of the computer systems, and also to the peripheral device being shared. The switch stores the current state o... | 04/26/1994 |
| 5307463 | Programmable controller communication module A module interfaces a programmable controller to several serial communication networks for the exchange of data carrying messages. A central processor controls the transfer of data between the module and other programmable controller components. The modul... | 04/26/1994 |
| 5307466 | Distributed programmable priority arbitration A distributed arbitration scheme for a communications bus wherein the bus interface modules decide among themselves who should next use the bus. The protocol is a common multiprocessor backplane bus interface for supporting multiprocessing, shared memory,... | 04/26/1994 |
| 5305439 | Method and apparatus for time-shared processing of different data word sequences Method and apparatus for time-shared processing of a sequence of principal data words having a constant period and at least one secondary word of a second sequence of secondary data words such that there is continuous processing of the secondary data word... | 04/19/1994 |
| 5305443 | Microprocessor with low power bus A microprocessor provides a bus state referred to as "loop-back". This state holds the data bus at valid logic levels, without use of resistors, after a read transaction has been completed and there are no pending bus transactions. When this state is ente... | 04/19/1994 |
| 5305460 | Data processor In a microcomputer having two program execution states including a supervisor state and a user state, there is disposed a flag or a register having such a flag indicating whether or not a RAM area used in the supervisor state can be used in the user state... | 04/19/1994 |
| 5303353 | Data transfer system A data bus has a bit length of 2 words, and is divided into two bit groups, each of which corresponds to one word. Therefore, the data bus can simultaneously transfer data of two words. A register, a data operation part of a CPU, a RAM and a ROM is connec... | 04/12/1994 |
| 5303382 | Arbiter with programmable dynamic request prioritization Methodology and circuitry for providing adaptable dynamic prioritization of a plurality of requestors for a shared resource with a plurality of prioritization commands selected according to the winning request of each arbitrage operation.... | 04/12/1994 |
| 5301275 | Data transfer system with variable data buffer size and programmable interrupt frequency A communication system including one or more host adapters connected to a host computer, each adapter having multiple serial communication ports for transferring data between the computer and several TTY devices. Several of the adapter's serial ports incl... | 04/05/1994 |
| 5301334 | Function expansion unit capable of supplying power to computer A system includes a computer main body, and an expansion unit detachably connected to the computer main body, for supplying a power to the computer main body and expanding a function of the computer. A power in the expansion unit is consumed in the expans... | 04/05/1994 |
| 5301332 | Method and apparatus for a dynamic, timed-loop arbitration In a computer system where maximum allowable latency periods are established for each of eight agents to access a shared buffer, the invention provides a timed loop that prevents starving out of any agent and a dynamically variable loop to prevent an allo... | 04/05/1994 |
| 5293632 | Method and apparatus for load shedding using a trainline monitor system A method for controlling power consumed by a plurality of subsystems on a multi-car train having a plurality of power supplies connected in parallel for supplying power to the subsystems. The train has a train wide communication network which includes a v... | 03/08/1994 |
| 5293490 | Data buffering device having simple data reading and/or storing function A data buffering device having a data buffer permitting data storage in a first storage area A while the area A is advanced over a predetermined number of storage areas of the buffer in a predetermined sequence and permitting data reading from a second st... | 03/08/1994 |
