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| Number | Title | Issue Date |
| 5230072 | System for managing hierarchical information in a digital data processing system A system for use in conjunction with a digital data processing system includes an applications program, a user interface and a hierarchy information management system. The applications program generates an information hierarchy including a plurality of hi... | 07/20/1993 |
| 5226141 | Variable capacity cache memory A variable length cache system keeps track of the amount of available space on an output device. The capacity of the cache system is continuously increased so long as it is less than the available output space on the output unit. Once the size of the cach... | 07/06/1993 |
| 5222220 | Microprocessor stack built-in guards The present invention is a method for a microprocessor such that when a call is made to a subroutine or an interrupt, a return address is stored in a "stack" memory (RAM) and also that a particular piece of hardware write the return address to an addition... | 06/22/1993 |
| 5220671 | Low-power consuming information processing apparatus There is disclosed a low-power consuming information processing apparatus having a storage unit for storing an application program of a main task, a main CPU capable of operating at a high speed for executing the application program, a sub-CPU for executi... | 06/15/1993 |
| 5218681 | Apparatus for controlling access to a data bus An apparatus for use with a host computing system for controlling access to a first data bus which is external of the host computing system and which first data bus is operatively connected with a second data bus internal of the host computing system. The... | 06/08/1993 |
| 5218684 | Memory configuration system A system permitting configuring of its total memory space includes a processor, an external operating device having a first address space and a bus coupling said central processing unit and the operating device. A starting address for the total memory spa... | 06/08/1993 |
| 5214768 | Mass data storage library A mass data storage unit includes a plurality of first data storage modules that form a mass information storage library, a data directory archive for maintaining a directory of the information contained on each data storage module, and data record/playba... | 05/25/1993 |
| 5210843 | Pseudo set-associative memory caching arrangement The invention provides a pseudo set-associative memory cacheing arrangement for use in a data processing system comprising a processor interfacing to a main memory and adapted to support a cache memory. The arrangement comprises a plurality of cache memor... | 05/11/1993 |
| 5210825 | Method and an apparatus for displaying graphical data received from a remote computer by a local computer In the present invention, a communication system is disclosed. The communication system comprises a remote computer 20 and a local computer 40, linked by communication link 12. The local computer 40 operates a conventional alphanumeric communication progr... | 05/11/1993 |
| 5210828 | Multiprocessing system with interprocessor communications facility A plurality of processors are connected to the interprocessor communications facility in the multiprocessing system of the invention. The interprocessor communications facility has arbitration circuitry, mailbox circuitry, and processor interrupt circuitr... | 05/11/1993 |
| 5206950 | Software development system and method using expanding outline interface A system and method for specifying a computer program. The specified computer program comprises a set of selected program objects, represented by a corresponding set of outline items arranged in a multilevel outline format. These outline items collectivel... | 04/27/1993 |
| 5206952 | Fault tolerant networking architecture A fault tolerant network for a plurality of computers includes a system for controlling access to shared peripherals. Access to the shared peripherals is coordinated among the computers by means of communication through a semaphore box. Each computer conn... | 04/27/1993 |
| 5206943 | Disk array controller with parity capabilities A disk array controller includes a local microprocessor, a bus master interface, a compatible interface, buffer memory and a disk interface. The controller includes a DMA controller between the microprocessor, the bus master interface, the compatibility i... | 04/27/1993 |
| 5202965 | Electronic system with a plurality of removable units The invention pertains to electronic data processing systems including a plurality of removable units that communicate with one another via a bus. To enable disconnection or connection of the removable units without interrupting the operation of the syste... | 04/13/1993 |
| 5197005 | Database retrieval system having a natural language interface A database retrieval system having a natural language interface is provided. A database developer creates a knowledge base containing a structural description and semantic description of an application database from which data is to be retrieved. A databa... | 03/23/1993 |
| 5193169 | Image data processing apparatus An image data processing apparatus has: a reading portion for reading an image of an original and outputting the image data thereon, an encoding portion for encoding the image data which has been output from the reading portion, an image memory for storin... | 03/09/1993 |
| 5193150 | Data transfer method, data transfer apparatus and information processing system A data transfer apparatus, in which when significant length data having a data length longer than the capacity of a communication bus is inputted/outputted through the communication bus into/from a data storage means, a part or the whole of the data trans... | 03/09/1993 |
| 5187782 | Data processing system An instruction is constituted by a plurality of words, minimum necessary information necessary for effective address calculation of an operand is stored in a leading word and a word or words containing an operation specification field (operation words) ar... | 02/16/1993 |
| 5185879 | Cache system and control method therefor A cache system which, when a cache is a bus master, puts a CPU in a standby state and makes effective a signal common to the CPU and cache and a signal decided only by the cache, or when the CPU is the bus master, makes effective the signal common to the ... | 02/09/1993 |
| 5185878 | Programmable cache memory as well as system incorporating same and method of operating programmable cache memory Methods and apparatus are disclosed for realizing an integrated cache unit (ICU) comprising both a cache memory and a cache controller on a single chip. The novel ICU is capable of being programmed, supports high speed data and instruction processing appl... | 02/09/1993 |
| 5179658 | Information processing apparatus An information processing apparatus having a scanner and a magnetic disk, both for supplying data to be stored, and an optical disk for storing the supplied data. The scanner supplies image data. The magnetic disk supplies code data such as document data ... | 01/12/1993 |
| 5179530 | Architecture for integrated concurrent vector signal processor Multiple special purpose processing units are provided in a vector signal processor for concurrent, parallel processing, particularly of complex vectors. The principal processing units are an execution unit, a data movement unit, a control/register unit, ... | 01/12/1993 |
| 5179668 | Signal processor The invention relates to a signal processor to be built into a controller or the like for receiving various input signals and generating control signals according to the input signals. The signal processor includes an internal bus interconnecting various ... | 01/12/1993 |
| 5175841 | Data processing device with multiple on-chip memory buses A microcomputer is disclosed which is specifically designed for computation-intensive applications. The microcomputer contains on-chip RAM and ROM, and has peripheral ports for access of external memory and input/output functions. The microcomputer has a ... | 12/29/1992 |
| 5165025 | Interlacing the paths after a conditional branch like instruction By interlacing the two program paths after the test part of a conditional branch, both program paths are available (with minimal delay) from a simple instruction fetch mechanism. Further, the interlacing of program paths continues only until one path ends... | 11/17/1992 |
| 5163153 | Low-power, standby mode computer A method and apparatus for configuring a computer in a low-power mode are provided. In the low-power mode, dynamic random access memory is refreshed by a battery powered system in order to maintain the memory contents. Low-power mode is entered by saving ... | 11/10/1992 |
| 5163141 | RAM lock device and method for a text entry system A memory system for use in a text entry system is provided. The system includes a retentive data memory and a system for locking a portion of the retentive memory and a key for unlocking the lockable portion of the memory to allow a predetermined number o... | 11/10/1992 |
| 5159672 | Burst EPROM architecture Circuitry which when combined with an EPROM in a single integrated circuit for connection to a microprocessor which provides suitable signals utilized by the additional circuitry to provude faster access to the code or data stored in the EPROM than can be... | 10/27/1992 |
| 5159183 | IC card An intrinsic cipher code peculiar to each IC card is written and stored in EEPROM serving as a writable non-volatile memory in an IC card, as well as a routine for performing collation with the intrinsic cipher code before a test program is executed being... | 10/27/1992 |
| 5157770 | Nonsynchronous DASD control Apparatus for controlling DASD in a manner that is not synchronous with channel operation, that is, transfer of commands and data are not limited to inter-record gap periods. A device interface processor controls which recording track is accessed by the D... | 10/20/1992 |
| 5155814 | Nonsynchronous channel/DASD communication system A control unit for DASD operation to transfer data between the device and a buffer and between a channel and a buffer. In that manner the channel and device are enabled to transfer data independently of each other. Mechanisms are provided for communicatio... | 10/13/1992 |
| 5155826 | Memory paging method and apparatus A method and apparatus to operate a paged memory system which uses only a single, predetermined address per page as a memory-mapped address. When the single memory-mapped address is accessed repeatedly by an unusual sequence, a sequence detector changes t... | 10/13/1992 |
| 5155817 | Microprocessor A microprocessor employs pipelined architecture and comprises a first execution processor for executing and processing a first kind of instructions among decoded instructions according to microprogram control, a second execution processor for executing an... | 10/13/1992 |
| 5151981 | Instruction sampling instrumentation A system and method for instrumenting the execution of instructions in an out-of-sequence execution machine. Instructions tagged with a preselected instruction identification number (IID) are identified. When an instruction having the preselected IID is e... | 09/29/1992 |
| 5146562 | Patient care communication system A patient care facility communication system with a plurality of communication terminals operatively coupled together for the transmission and receipt of messages, includes a program providing a message composition facility by which an operator may select... | 09/08/1992 |
| 5146605 | Direct control facility for multiprocessor network Control panel function is provided to bus units coupled together by an I/O bus. At least one bus unit has the capability to issue control commands through the bus to one or more other bus units. A control facility is integrated into bus units, and makes f... | 09/08/1992 |
| 5146560 | Apparatus for processing bit streams Apparatus for processing a stream of bits including a hardware comparator that compares first predetermined bits of the stream, comparison input means to provide a table of comparison values to said hardware comparator for comparison with said predetermin... | 09/08/1992 |
| 5136707 | Reliable database administration arrangement In a distributed system, such as a PBX (FIG. 1), which uses a database for its operation, a master copy (22) of the database having a first format is stored at a central node (10) and cache copies (32) of database portions (24) but having a different form... | 08/04/1992 |
| 5133076 | Hand held computer A hand held computer of a type used for such activities as taking inventory, recording signatures on delivery, keeping a route agenda, etc. has a large screen and preferably is without a built in keyboard. The tablet type computer is thin in profile, ligh... | 07/21/1992 |
| 5131089 | Solid state disk drive emulation A system for causing a computer solid state memory to emulate a magnetic disk mounted in a disk drive. In the preferred embodiment, the system includes two removable RAM cards and two ROM's. Program instructions encoded in firmware in the system BIOS tran... | 07/14/1992 |
