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| Number | Title | Issue Date |
| 8188573 | Nitride semiconductor structure A nitride semiconductor substrate and a method for manufacturing the same are provided. The nitride semiconductor substrate includes an epitaxy substrate, a nitride pillar layer, a nitride semiconductor layer, and a mask layer. The nitride pillar layer includes a pl... | 05/29/2012 |
| 8174013 | Semiconductor device, method for manufacturing the semiconductor device, and display device A semiconductor device includes a semiconductor layer having a channel region, an impurity layer having a source region and a drain region, and a gate electrode provided so as to face the semiconductor layer with a gate insulating film interposed therebetween. The s... | 05/08/2012 |
| 8174010 | Unified test structure for stress migration tests A unified test structure which is applicable for all levels of a semiconductor device including a current path chain having a first half chain and a second half chain, wherein each half chain comprises lower metallization segments, upper metallization segments, an i... | 05/08/2012 |
| 8168964 | Semiconductor device using graphene and method of manufacturing the same A semiconductor graphene is used for a channel layer, and a metal graphene is used for electrode layers for a source, a drain, and a gate which serve as interconnections as well. An oxide is used for a gate insulating layer. The channel layer and the electrode layer... | 05/01/2012 |
| 8164144 | Semiconductor device and manufacturing method thereof A semiconductor device includes a semiconductor layer on an insulating layer, and a first partially depleted transistor and a first diode in the semiconductor layer. The first transistor has a first gate electrode above the semiconductor layer via an insulating film... | 04/24/2012 |
| 8164102 | Semiconductor light emitting device A semiconductor light emitting device may include a first lead; a second lead; a first semiconductor light emitting element mounted on the first lead, being configured to emit a light having an optical emission spectrum no more than 400 nm from a light extraction su... | 04/24/2012 |
| 8154010 | Memory device and method of fabricating the same A memory device includes a first electrode, a second electrode spaced apart from the first electrode and a nanotube or nanowire network disposed between the first electrode and the second electrode, having a stacked structure of a P-type network and an N-type networ... | 04/10/2012 |
| 8138501 | Switching element and manufacturing method thereof Disclosed is a switching element provided with a gate dielectric film and an active layer disposed in contact with the gate dielectric film. The active layer includes carbon nanotubes, and the gate dielectric film includes non-conjugated polymer containing an aromat... | 03/20/2012 |
| 8134204 | DEMOS transistors with STI and compensated well in drain A drain extended MOS (DEMOS) transistor with an element of field oxide separating the drain contact from the gate, and a compensation region of opposite polarity in the drain under the gate, is disclosed. The inventive DEMOS may be fabricated in a CMOS IC without ad... | 03/13/2012 |
| 8129704 | Non-volatile resistive-switching memories Non-volatile resistive-switching memories are described, including a memory element having a first electrode, a second electrode, a metal oxide between the first electrode and the second electrode. The metal oxide switches using bulk-mediated switching, has a bandga... | 03/06/2012 |
| 8115274 | Fuse structure and method for manufacturing same A fuse structure includes a substrate, a fuse conductive trace disposed closer to a first chip surface than to a second chip surface facing away from the first chip surface, a metallization layer on the substrate disposed on a side of the fuse conductive trace facin... | 02/14/2012 |
| 8084849 | Integrated circuit package system with offset stacking An integrated circuit package system includes: providing an interposer having a bond pad and a contact pad; mounting the interposer in an offset location over a carrier with an exposed side of the interposer coplanar with an edge of the carrier; connecting an electr... | 12/27/2011 |
| 8063484 | Semiconductor device and heat sink with 3-dimensional thermal conductivity A semiconductor device, comprising: a semiconductor element 20 having a rectangular two-dimensional geometry and serving as a heat source; and a heat sink section 25 having the semiconductor element 20 mounted thereon, wherein a relation among t... | 11/22/2011 |
| 8039907 | Semiconductor device and method for fabricating the same A transistor, comprising a first gate structure formed on a substrate, and having a stacked structure of a first gate electrode and a first gate hard mask, a first gate spacer formed on sidewalls of the first gate structure, a second gate structure having a stacked ... | 10/18/2011 |
| 8022544 | Chip structure A chip structure includes a semiconductor substrate, an interconnecting metallization structure, a passivation layer, a circuit layer and a bump. The interconnecting metallization structure is over the semiconductor substrate. The passivation layer is over the inter... | 09/20/2011 |
| 8022543 | Underbump metallurgy for enhanced electromigration resistance A first metallic diffusion barrier layer is formed on a last level metal plate exposed in an opening of a passivation layer. Optionally, a metallic adhesion promotion layer is formed on the first metallic diffusion barrier layer. An elemental metal conductive layer ... | 09/20/2011 |
| 7973415 | Manufacturing process and structure of through silicon via A through silicon via reaching a pad from a second surface of a semiconductor substrate is formed. A penetration space in the through silicon via is formed of a first hole and a second hole with a diameter smaller than that of the first hole. The first hole is forme... | 07/05/2011 |
| 7968802 | Printed circuit board with differential traces A printed circuit board (PCB) includes a differential pair having a first differential trace and a second differential trace, a first via having an upper cap and a lower cap, and a second via having an upper cap and a lower cap. The first differential trace includes... | 06/28/2011 |
| 7935626 | Semiconductor device and method for manufacturing the same In a manufacturing process of a semiconductor device, electroplating and CMP have had a problem of increase in manufacturing costs for forming a wiring. Correspondingly, an opening is formed in a porous insulating film after a mask is formed thereover, and a conduct... | 05/03/2011 |
| 7932534 | High light extraction efficiency solid state light sources A solid state light source includes a substrate having a top surface and a bottom surface, and at least one optically active layer on the top surface of the substrate. At least one of the top surface, the bottom surface, the optically active layer or an emission sur... | 04/26/2011 |
| 7928574 | Semiconductor package having buss-less substrate A ball grid array device with an insulating substrate (110) having metal traces (106, for example copper, about 18 μm thick) with sidewalls (108) at right angles to the trace top. The traces are grouped in a first (120) and a second set ... | 04/19/2011 |
| 7928452 | GaN-based semiconductor light-emitting element, light-emitting element assembly, light-emitting apparatus, method of manufacturing GaN-based semiconductor light-emitting element, method of driving GaN-based semiconductor light-emitting element, and image display apparatus A GaN-based semiconductor light-emitting element includes a first GaN-based compound semiconductor layer of n-conductivity type, an active layer, a second GaN-based compound semiconductor layer of p-conductivity type, a first electrode electrically connected to the ... | 04/19/2011 |
| 7923833 | Semiconductor module A semiconductor module 10 includes a ceramic substrate having a front surface on which a semiconductor element 12 is mounted and a rear surface on the opposite side of the front surface, a front metal plate 15 joined to the front surface, a rear... | 04/12/2011 |
| 7923797 | Solid-state image sensing device driving method and solid-state image sensing apparatus A method of driving a solid-state image sensing device comprises plural photoelectric conversion devices arranged in rows and columns perpendicular to the rows, VCCDs through which charges generated by the photoelectric conversion devices are transferred in the colu... | 04/12/2011 |
| 7919843 | Semiconductor device and its manufacturing method There is provided a semiconductor device 10 including a solder resist 16 for protecting a wiring pattern 14 electrically connected to a semiconductor chip 11 via an internal connection terminal 12, characterized in that the solder ... | 04/05/2011 |
| 7919789 | Lateral light-emitting diode backlight module A lateral light-emitting diode backlight module includes a base, a circuit board, and at least a light emitting diode wherein the base having a heat conductor, the circuit board having a conductive pad formed on a surface thereof, and the circuit board disposed on t... | 04/05/2011 |
| 7919359 | Semiconductor mounting substrate and method for manufacturing the same A semiconductor mounting substrate according to the present invention comprises: a substrate; a semiconductor device, mounted on this substrate; solder bumps, which connect the semiconductor device and the substrate; a first resin, filled in a space between the semi... | 04/05/2011 |
| 7919847 | Semiconductor wafer, semiconductor device, and semiconductor device manufacturing method A semiconductor wafer includes a plurality of chip areas, a scribe line area, a bonding pad, a probing pad, and a pad connection wiring. The plurality of chip areas are configured to be arranged in a matrix form. The scribe line area is configured to separate the pl... | 04/05/2011 |
| 7915153 | Passivation film and method of forming the same A passivation film and a method of forming the same are provided, the passivation film being used in a plasma display panel etc. In the passivation film, a first MgO layer, an intervening layer, and a second MgO layer are laminated and a laser is then irradiated to ... | 03/29/2011 |
| 7910482 | Method of forming a finFET and structure A method for processing a substrate comprising at least a buried oxide (BOX) layer and a semiconductor material layer is provided. The method includes etching the semiconductor material layer to form a vertical semiconductor material structure overlying the BOX laye... | 03/22/2011 |
| 7910971 | Methods of forming vertical field effect transistors, vertical field effect transistors, and dram cells A method of forming a vertical field effect transistor includes etching an opening into semiconductor material. Sidewalls and radially outermost portions of the opening base are lined with masking material. A semiconductive material pillar is epitaxially grown to wi... | 03/22/2011 |
| 7906777 | Semiconductor thin film and method for manufacturing same, and thin film transistor The present invention provides a semiconductor thin film which can be manufactured at a relatively low temperature even on a flexible resin substrate. As a semiconductor thin film having a low carrier concentration, a high Hall mobility and a large energy band gap, ... | 03/15/2011 |
| 7906859 | Semiconductor device A semiconductor device includes a molding resin layer and a semiconductor element encapsulated with the molding resin layer. The molding resin layer has an opening. A surface of the semiconductor element is partially exposed outside the molding resin layer through t... | 03/15/2011 |
| 7902617 | Forming a thin film electric cooler and structures formed thereby Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a first plurality of openings through a first surface of a substrate, forming a p-type TFTEC material within the first plurality of openings, forming a second ... | 03/08/2011 |
| 7902015 | Array of nanoscopic MOSFET transistors and fabrication methods A nanoscopic transistor is made by forming an oxide layer on a semiconductor substrate, applying resist, patterning the resist using imprint lithography to form a pattern aligned along a first direction, applying a first ion-masking material over the pattern, select... | 03/08/2011 |
| 7902651 | Apparatus and method for stacking integrated circuits A multi-chip stack module provides increased circuit density for a given surface chip footprint. The multi-chip stack module comprises support structures alternating with standard surface mount type chips to form a stack wherein the support structures electrically i... | 03/08/2011 |
| 7902602 | Organic thin film transistor with stacked organic and inorganic layers The present invention provides an organic thin film transistor and method for fabricating the same. The organic thin film transistor has a substrate and a gate electrode that is positioned on the substrate. A gate insulator has a stacked structure comprising an inor... | 03/08/2011 |
| 7902555 | Semiconductor device A hetero semiconductor corner region, which is a current-concentration relief region that keeps a reverse bias current from concentrating on the convex corner, is arranged in a hetero semiconductor region. Thereby, a current concentration on the convex corner can be... | 03/08/2011 |
| 7902600 | Metal oxide semiconductor device A metal oxide semiconductor device comprising a substrate, at least an isolation structure, a deep N-type well, a P-type well, a gate, a plurality of N-type extension regions, an N-type drain region, an N-type source region and a P-type doped region is provided. The... | 03/08/2011 |
| 7902625 | Metal-gate thermocouple A metal gate thermocouple is provided. The thermocouple is configured to measure local temperatures of a device. The thermocouple is a passive device which senses temperature using the thermoelectric principle that when two dissimilar electrically conductive materia... | 03/08/2011 |
