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| Number | Title | Issue Date |
| 4609995 | Priority controller A priority controller includes a pair of read only memories and a register. The register stores information identifying a request circuit to which priority has recently been granted. Corresponding locations of the two read only memories store identical da... | 09/02/1986 |
| 4593350 | Distributed processor with periodic data transfer from each memory to like addresses of all other memories A plurality of computer stations each includes a data processing computer capable of having its data processing function inhibited or halted by a halt signal applied to a halt input terminal, and each also includes a random access memory (RAM). The plural... | 06/03/1986 |
| 4580239 | Remote station of a computer system The present invention is an improvement to a station at a remote location from a distant computer which communicates at a predetermined rate prior to said improvement by way of telephone lines. A modem is connected to the telephone line which converts sig... | 04/01/1986 |
| 4569015 | Method for achieving multiple processor agreement optimized for no faults An originating processor broadcasts a value in a message with its unforgeable signature to all n active processors, including itself. Receiving processors in the network pass such a message on with their own unforgeable signatures to all active processors... | 02/04/1986 |
| 4564900 | Multiprocessor computer system A multiprocessor computer system wherein memory buses of separate central processing unit systems are interfaced to an intermemory communication network for transfer of data between memories of said separate central processing unit systems. The intermemor... | 01/14/1986 |
| 4562532 | Main storage configuration control system A data processing system provided with a main storage unit comprising: a main storage including a plurality of configuration units and a main storage controller for selecting one of the configuration units of the main storage and for controlling reading a... | 12/31/1985 |
| 4558412 | Direct memory access revolving priority apparatus In a terminal system comprising a central processor subsystem, a memory subsystem and a plurality of peripheral subsystems, all connected in common to a system bus, the system bus timing is divided into a plurality of fixed times including a central proce... | 12/10/1985 |
| 4554627 | Data processing system having a unique micro-sequencing system A data processing system which handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses, the latter being translated into physical addresses by unique translation means. Th... | 11/19/1985 |
| 4553201 | Decoupling apparatus for verification of a processor independent from an associated data processing system In a data processing system having a plurality of CPUs, each CPU is operatively connected to other portions of the data processing system through a system interface unit. The CPU includes a cache memory, an execution unit, and a control unit. Further, eac... | 11/12/1985 |
| 4549263 | Device interface controller for input/output controller A device interface controller provides a sophisticated communication link between a central processor and peripheral digital apparatus. The device interface controller provides simultaneous read and write operations with the peripheral digital apparatus. ... | 10/22/1985 |
| 4546429 | Interactive communication channel An interactive communications channel (ICC) for providing a digital computer with high-performance multi-channel interfaces. Sixteen full duplex channels can be serviced in the ICC with the sequence or scan pattern being programmable and dependent upon th... | 10/08/1985 |
| 4546433 | Arrangement for processing data in a two-dimensional array A data processing arrangement is designed to handle two dimensional data arrays. An operation is performed on each element in th data array which is partially dependent on the nature of the neighboring data elements which surround it. In this way particul... | 10/08/1985 |
| 4545013 | Enhanced communications network testing and control system A network control and test system for application to data communications networks. In a first mode of operation, the system learns the network configuration automatically and builds a table describing the network configuration. In a second mode of operati... | 10/01/1985 |
| 4545011 | Enhanced communications network testing and control system A network control and test system for application to data communications networks. In a first mode of operation, the system learns the network configuration automatically and builds a table describing the network configuration. In a second mode of operati... | 10/01/1985 |
| 4545030 | Synchronous clock stopper for microprocessor A synchronous clock stopper circuit for inhibiting clock pulses to a microprocessor in response to a stop request signal, and for reinstating the clock pulses in response to a start request signal thereby to conserve power consumption of the microprocesso... | 10/01/1985 |
| 4543626 | Apparatus and method for controlling digital data processing system employing multiple processors A control arrangement for coordinating operations of multiple processors in a multiprocessor system in response to a command. Each command is associated with a route comprising a sequence of route vectors, each identifying an operation to be performed to ... | 09/24/1985 |
| 4539635 | Pipelined digital processor arranged for conditional operation A pipelined digital processor includes a common data and control bus and a source (100 or 105) of instructions and data words. An arithmetic section (110) processes one data word with another data word through selected processing subsections (112, 115, 11... | 09/03/1985 |
| 4539652 | Networks for data communication A mechanized system distributing the access, test and communication functions to the point of testing, typically the centralized switching facility serving the telephone loops and equipment to be tested. Computer (200) stores information about each subscr... | 09/03/1985 |
| 4538226 | Buffer control system In a data processing system, an apparatus for controlling the delivery of write data from a processing unit with a buffer device to a main store. The delivery of data from the buffer device to the main store is delayed until a counter detects a predetermi... | 08/27/1985 |
| 4536856 | Method of and apparatus for controlling the display of video signal information A video signal display control method and apparatus provide the display control functions for LCD-type or other similar display devices to be attached as output display units to an external microcomputer or other control systems that provide output video ... | 08/20/1985 |
| 4535420 | Circular-queue structure Apparatus for producing a circular-queue structure which permits interfacing between a high speed mini-computer and a relatively slow speed microprocessor via a common memory and with multi-device, asynchronous handling capability. The structure also perm... | 08/13/1985 |
| 4528625 | Input/output instruction execution in microcomputer A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program ROM and data RAM, with separate address and data paths for program and data. An external program address bus allows the alternative... | 07/09/1985 |
| 4527235 | Subscriber terminal polling unit A subscriber services system polling unit in which microprocessors, each primarily responsible for controlling the polling of half the subscriber terminals, may be switched to also control the polling of the other half of the subscriber terminals.... | 07/02/1985 |
| 4523295 | Power loss compensation for programmable memory control system An arrangement for storing user programmed system timing information in a microprogrammable system in the event of a power outage. The system includes a static random access memory (RAM) for periodically storing microprocessor-generated timing information... | 06/11/1985 |
| 4521850 | Instruction buffer associated with a cache memory unit Apparatus and method for providing an improved instruction buffer associated with a cache memory unit. The instruction buffer is utilized to transmit to the control unit of the central processing unit a requested sequence of data groups. In the current in... | 06/04/1985 |
| 4521848 | Intersystem fault detection and bus cycle completion logic system An error detection system is disclosed for not only indicating but eliminating certain errors which may occur during the transfer of information between communication busses in a data processing system wherein plural communication busses each provide a co... | 06/04/1985 |
| 4520454 | Makeready system Apparatus and method are disclosed for making ready a multi-unit, multi-web printing press. Data is entered into a computer memory representing the number of sections of a publication to be printed, the number of pages for each section and which pages of ... | 05/28/1985 |
| 4518961 | Universal paging device with power conservation A battery powered, adaptive signal decoder is disclosed which is capable of processing detected encoded signals in accordance with a plurality of decoding schemes. The decoder has an equivalent microcomputer implementation. Energy conservation means opera... | 05/21/1985 |
| 4516219 | Address designating method of memory and apparatus therefor An address designating method of a memory is performed by dividing the addresses of the memory to row addresses and column addresses. The writing of data in the memory is performed by the following steps. Namely, while the row addressing is maintained in ... | 05/07/1985 |
| 4514824 | Byte-oriented line adapter system A line adapter system for handling byte-oriented data transfers between remote data terminals and I/O subsystem. Working in conjunction with a controlling microprocessor, the line adapter provides input output means for regulating the baud rate of transmi... | 04/30/1985 |
| 4512027 | Electronic calculating device with faculties of detecting reproduction level of data applied thereto An electronic calculating machine includes a control circuit for receiving digital calculation information recorded in an audio tape to be applied to the machine. The control circuit comprises a circuit for forming the information to pulse signals, a circ... | 04/16/1985 |
| 4510580 | Programmable sequence controller A programmable sequence controller using a technique called microprogramming, including a microprogram memory having a plurality of memory sections each storing a set of microinstructions corresponding to the command word of a sequence instruction. The op... | 04/09/1985 |
| 4509119 | Method for managing a buffer pool referenced by batch and interactive processes Method for managing a buffer pool shared by sequential and random processes. A data base manager includes a buffer manager which: (1) maintains a normal least recently used (LRU) buffer chain and a sequential LRU buffer chain, the sequential LRU buffer ch... | 04/02/1985 |
| 4509136 | Teller machine with preset abilities A teller machine includes numeral keys, function keys, a central processor unit, and a printer for printing out transaction data onto a desired bill. A preset ability is employed by the teller machine so that a bill issuance number is limited at operator'... | 04/02/1985 |
| 4507732 | I/O subsystem using slow devices An I/O subsystem uses a peripheral-controller for handling data transfer operations between a host computer and a plurality of peripheral terminals. The peripheral controller is made of (a) a universal processor, which generates instructions for executing... | 03/26/1985 |
| 4506324 | Simulator interface system A linkage between a host computer and a plurality of external devices, such s a simulator system, utilizes a distributed processing network of individual data processors to process, control, and position data for transmission to and from said host computer... | 03/19/1985 |
| 4506323 | Cache/disk file status indicator with data protection feature A data processing system has a host processor, a RAM, a cache memory for storing segments of data, a plurality of disk drive devices and a storage control unit for controlling data transfers, data from the host processor being written to the cache memory ... | 03/19/1985 |
| 4504903 | Central processor with means for suspending instruction operations A central processor for use in a data processing system that is adapted for processing sequences of characters. Information identifying a string of characters to be examined, including an initial memory location of the first character in the sequence and ... | 03/12/1985 |
| 4504907 | High speed data base search system A high speed data base search system which contains a general purpose computer coupled to a special purpose processor called the High Speed Search Function or HSSF. The HSSF may be external to the computer having a standard Input/Output communication path... | 03/12/1985 |
| 4504925 | Self-shifting LIFO stack A self-shifting last-in-first-out stack for a data processing system, including a plurality of parallel linear arrays of data storage cells interconnected for enabling stored data to be shifted to or from an adjacent cell within the same array. The parall... | 03/12/1985 |
