U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

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...that the Band-Aid Bandage was invented by a Johnson & Johnson employee whose wife had cut herself? Earl Dickson's wife was rather accident prone, so he set out to develop a bandage that she could apply without help. He placed a small piece of gauze in the center of a small piece of surgical tape, and what we know today as the Band Aid bandage was born!

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Examiner: Lam, David


Primary examiner statistics: 899 patents; average approval time: 898 days
Assistant examiner statistics: 371 patents; average approval time: 524 days

Patents as Primary Examiner (view all)

Patent No. Patent Title:
8189392 Page buffer circuit
8189394 Page buffer circuit of nonvolatile memory device and method of op...
8189405 Data readout circuit and semiconductor memory device
8184474 Asymmetric SRAM cell with split transistors on the strong side
8184488 Systems and methods for controlling integrated circuit operation ...
8179715 8T SRAM cell with four load transistors
8181190 Optical disc apparatus
8176232 Dedicated interface to factory program phase-change memories
8169836 Buffer control signal generation circuit and semiconductor device
8169835 Charge trapping memory cell having bandgap engineered tunneling s...
8164970 Third dimensional memory with compress engine
8164960 Write buffering systems for accessing multiple layers of memory i...
8164952 Nonvolatile memory device and related method of programming
8164945 8T SRAM cell with two single sided ports
8164948 Spintronic devices with integrated transistors
8161244 Multiple cache directories
8159893 Data flow control in multiple independent port
8161233 Multi-stream restore system and method
8159863 6T SRAM cell with single sided write
8154933 Mode-register reading controller and semiconductor memory device
8154919 Method of reading nonvolatile memory device and nonvolatile memor...
8151037 Interface for solid-state memory
8149618 Over-sampling read operation for a flash memory device
8149541 System for controlling contact location during TFC touchdown and ...
8144435 Cost reduced microactuator suspension
8140747 Operating method for a memory subsystem and devices for executing...
8135913 Mixed multi-level cell and single level cell storage device
8134873 Flash memory device and programming/erasing method of the same
8130535 Flexible word-line pulsing for STT-MRAM
8125833 Adaptive dynamic reading of flash memories
8120979 Semiconductor memory devices having hierarchical bit-line structu...
8120878 Tubular stiffening rails for head suspension components
8122212 Method and apparatus for logical volume management for virtual ma...
8116143 Method of erasing memory cell
8116130 Integrated circuits with nonvolatile memory elements
8111532 Method and apparatus for CAM with redundancy
8111580 Multi-phase duty-cycle corrected clock signal generator and memor...
8111567 Semiconductor device
8111578 Memory devices having redundant arrays for repair
8108623 Poll based cache event notifications in a distributed cache

Patents as Assistant Examiner (view all)

Patent No. Patent Title:
6538913 Method for operating a ferroelectric memory configuration and a ...
6515925 Balanced sense amplifier control for open digit line architecture...
6510085 Method of channel hot electron programming for short channel NOR ...
6510080 Three terminal magnetic random access memory
6504766 System and method for early write to memory by injecting small vo...
6501693 Semiconductor memory device allowing easy characteristics evaluat...
6501684 Integrated circuit having an EEPROM and flash EPROM
6493258 Magneto-resistive memory array
6487141 Digital delay, digital phase shifter
6483756 Sequence circuit and semiconductor device using sequence circuit
6477088 Usage of word voltage assistance in twin MONOS cell during progra...
6473356 Low power read circuitry for a memory circuit based on charge ...
6445631 Non-volatile latch with program strength verification
6438067 Clock generating circuit ensuring a wide lock-allowing frequency ...
6430092 Memory device with booting circuit capable of pre-booting before ...
6426897 Method of erasing a flash memory device
6424560 Semiconductor integrated circuit device and information processin...
6424562 Read/write architecture for MRAM
6421291 Semiconductor memory device having high data input/output frequen...
6411563 Semiconductor integrated circuit device provided with a logic cir...
6407959 Microcomputer and microprocessor having flash memory operable fro...
6404672 Magnetic element and magnetic memory device
6404673 Magnetic memory device and method of reading data in magnetic mem...
6404689 Method and structure for hiding a refresh operation in a DRAM hav...
6404686 High performance, low cell stress, low power, SOI CMOS latch-type...
6400643 Semiconductor storage device with suppressed power consumption an...
6396763 DRAM having a reduced chip size
6396746 Semiconductor memory device
6392955 Circuit for eliminating idle cycles in a memory device
6392934 Method for reading and writing a data storage medium comprising a...
6388927 Direct bit line-bit line defect detection test mode for SRAM
6385104 Semiconductor memory device having a test mode decision circuit
6385091 Read reference scheme for non-volatile memory
6381162 Circuitry and method for controlling current surge on rails of ...
6377504 High-density memory utilizing multiplexers to reduce bit line pit...
6377483 Semiconductor memory device having improved memory cell and bit l...
6377491 Non-volatile memory for storing erase operation information
6373742 Two side decoding of a memory array
6373774 Semiconductor memory device with bank configuration
6373748 Nonvolatile semiconductor memory
 
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