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...During the Civil War, the Confederacy established its own Patent Office which issued 266 patents, a third of which concerned implements of war.
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| Number | Title | Issue Date |
| 7390515 | Methods of treating viral infections using berry juice fractions The present invention concerns the use as anti-viral agents of isolated fractions from berry juice of the plant genus Vaccinium. Two specific fractions are provided: (a) polymeric material having a molecular weight≧12,000; and (b) proanthocyanidins-containi... | 06/24/2008 |
| 7105187 | Method for obtaining taxanes A method for obtaining a taxane by which a taxane is isolated from a growth medium, such as soil, in which a taxane-producing plant has grown. ... | 09/12/2006 |
| 7090872 | Antioxidant, skin preparation for external use, cosmetic and food The invention relates to antioxidants that make effective use of acerola seeds, which have conventionally been discarded, that have high safety and excellent antioxidative effect in skin preparations for external use, cosmetics, and food, and that contain acerola se... | 08/15/2006 |
| 7015032 | Intermittent immersion vessel apparatus and process for plant propagation A plant micropropagation apparatus and process is provided in which a support platform for vessels containing a liquid growth media are periodically pivoted which brings about an intermittent immersion of the plant tissue/growth substrate in the growth media. The mo... | 03/21/2006 |
| 4807179 | Method and device for recording analog parameters on a static digital memory A method and apparatus are provided for data storage in, for example, a black box for an aircraft. A static digital memory is divided into three portions, A, B and C. Data is read into successive sequential portions of wrap-around memory portion A. When a... | 02/21/1989 |
| 4800488 | Method of propagating resource information in a computer network A method of propagating resource information among computers of a computer network in a fully distributed (or decentralized) fashion. A solicit message from a client one of the computers is transmitted to one or more prescribed server ones of the computer... | 01/24/1989 |
| 4799146 | System for displaying graphic information on video screen employing video display processor A system which interprets the contents of address and data fields provided by a central processing unit 1 which controls the display. The address fields are selectively interpreted to obtain a direct access by the central processing unit to a general syst... | 01/17/1989 |
| 4794518 | Pipeline control system for an execution section of a pipeline computer with multiple selectable control registers in an address control stage A pipeline control system for a computer in which predetermined tag data or micro instructions are stored in a plurality of tag registers while executing a first sequence of instructions in order to repetitively execute a flow of processing which is based... | 12/27/1988 |
| 4792897 | Address translation unit for translation of virtual address to real address using translation tables of multi-level hierarchical structure An extended address translation equipment wherein an address translation buffer has entries each provided with a record of translation table addresses of each level, thereby eliminating the need for accessing the translation table up to a portion consiste... | 12/20/1988 |
| 4789927 | Interleaved pipeline parallel processing architecture A system for processing of data wherein the data is inputted over time into the system such that a second packet of data is inputted before a first packet of data, the system comprising a first processor coupled to a second processor, the first processor ... | 12/06/1988 |
| 4787060 | Technique for determining maximum physical memory present in a system and for detecting attempts to access nonexistent memory A method for determining the maximum amount of physical memory present in a data processing system that can be configured to have one or more memory modules where the memory modules may be one of several types having different amounts of memory locations.... | 11/22/1988 |
| 4764863 | Hardware interpreter for finite state automata Apparatus and method for monitoring transactions on a high speed interface us and for selectively storing information about such transactions together with the time of such transaction and the state of the automaton. The apparatus comprises two parallel me... | 08/16/1988 |
| 4763250 | Paged memory management unit having variable number of translation table levels In a paged memory management unit (PMMU), a translation control (TC) register contains a set of table indexes which define the number of bits of the logical address to be used to access the translation table at the respective levels. The TC register also ... | 08/09/1988 |
| 4763252 | Computer entry system for predetermined text data sequences An apparatus for facilitating entry of pre-defined sequences of data characters into a computer or computer-controlled system, and preferably connected between the computer and its keyboard. Each data sequence is identified by a multi-character alphanumer... | 08/09/1988 |
| 4758951 | Method for translating virtual addresses into real addresses A disk operating system converts virtual storage space locations of one or more processes into real disk or core memory storage space locations of a computer system. Real and virtual storage space are divided into equal sized pages. Real storage pages are... | 07/19/1988 |
| 4757470 | Pattern generation for a graphics display A display subsystem having a graphics capability includes a bit map memory for storing bits, each bit representing a displayed pixel. A read only memory stores words, each word representative of a pixel of a selected pattern which is used to fill out an a... | 07/12/1988 |
| 4750115 | Data communication system between two different data transmission systems A data communication system for the communication between two different data transmission systems, the SDT system and the RDT system. The SDT system includes a host CPU having an output terminal for repeatedly producing first data in a predetermined seque... | 06/07/1988 |
| 4747046 | Mechanism for comparing two registers and storing the result in a general purpose register without requiring a branch In a computer device, an instruction set which uses a two-instruction sequence to store the result of a comparison is provided. The two-instruction sequence, which uses no branch instructions, does not need to wait for condition resolution before storing ... | 05/24/1988 |
| 4744025 | Arrangement for expanding memory capacity An expandable memory connected to a central processing unit includes several memory modules which transfer configuration signals serially to the central processing unit by way of an interface circuit. The interface circuit also selects ones of the memory ... | 05/10/1988 |
| 4740913 | Ornamental display device for electronic dictionary A display device for an electronic dictionary such as an electronic translator or an electronic language dictionary is featured by displaying ornamental patterns formed with ornamental data and word data when the dictionary is left unoperated. The display... | 04/26/1988 |
| 4740911 | Dynamically controlled interleaving A data processing system in which interleaving among memory controllers may be controlled. The interleaving is carried out on a double-word basis, and the state of the double-word address bit is used to select the bus address of the memory controller in w... | 04/26/1988 |
| 4740895 | Method of and apparatus for external control of computer program flow This apparatus controls the execution and content of computer programs in equipment containing a computer by causing the transfer of program data elements, including computer instructions, with a memory means of the apparatus, wherein the selection of dat... | 04/26/1988 |
| 4733348 | Virtual-memory multiprocessor system for parallel purge operation A virtual memory control multiprocessor system has a plurality of processors each having a translation lookaside buffer (TLB). A purge request source processor commonly supplies a purge request signal to other processors so as to cause them to perform TLB... | 03/22/1988 |
| 4733350 | Improved purge arrangement for an address translation control system An address translation control system comprising an address translation buffer having a plurality of entries each including at least a valid flag, a logical address field, and a physical address field, a memory array having copies of at least the valid fl... | 03/22/1988 |
| 4731748 | Pocket computer with means for checking the detachable memory module before and after power interruption An electronic apparatus such as a pocket computer is of the type in which a detachable memory module can be operatively coupled. Just upon interruption of power, the apparatus generates indefinite information such as random number, time information, or th... | 03/15/1988 |
| 4731725 | Data processing system which suggests a pattern of medical tests to reduce the number of tests necessary to confirm or deny a diagnosis A data processing system for use in a total medical image diagnosis comprising a central processing unit, a first memory connected to the central processing unit for storing a plurality of types of fundamental data used for constructing a decision tree, a... | 03/15/1988 |
| 4727479 | Allocation circuit for parallel busses of data processing systems An allocation system for the use of a data processing system where plural user systems of the data processing system gain access to parallel busses of the data processing system in a sequential manner based on a priority determination. The priority determ... | 02/23/1988 |
| 4727475 | Self-configuring modular computer system with automatic address initialization An initial polling sequence for configuring a modular computer system employing a system bus for interconnecting the CPU and various modules attached to the bus. At the beginning of the polling sequence, a bus base address register in each module is prese... | 02/23/1988 |
| 4723204 | Dynamic RAM refresh circuit A dynamic RAM refresh circuit provides the interface for timely refresh of up to 64K of RAM memory while simultaneously providing for minimal disruption of a CPU's access of that RAM memory. Circuitry is also provided to permit interlock control for times... | 02/02/1988 |
| 4722047 | Prefetch circuit and associated method for operation with a virtual command emulator A prefetch circuit for use with a memory including a storage register for receiving a command from the memory, a decoding circuit for decoding the command to determine the identification of an index register contained within the command, and a fetch circu... | 01/26/1988 |
| 4720783 | Peripheral bus with continuous real-time control A digital data processing system wherein large amounts of digital data are transferred from a source that is coupled to the internal bus of a host CPU to a data receiving device by cooperation between the host CPU and a microprocessor. A multiplexer has o... | 01/19/1988 |
| 4719592 | Sequence generator A sequence generator for producing a sequence of binary numbers, comprises a counter, a priority encoder which encodes the contents of the counter, a memory addressed by the output of the encoder, an output register, and a logic circuit for modifying the ... | 01/12/1988 |
| 4718005 | Distributed control of alias name usage in networks Computer systems linked to nodes in a communication network communicate directly with each other to establish name associations for entities (e.g. programs, storage files, etc.) susceptible of being shared across the network, and thereafter communicate fu... | 01/05/1988 |
| 4716523 | Multiple port integrated DMA and interrupt controller and arbitrator Both DMA access and character interrupt driven access modes of service are provided to multiple communication ports by an integrated arbitration DMA/interrupt controller utilizing its own resident randomly accessible memory. Pipelined logic control archit... | 12/29/1987 |
| 4714993 | Apparatus and method for effecting dynamic address translation in a microprocessor implemented data processing system The performance of a multi-microprocessor implemented data processing system that emulates a mainframe system is enhanced and optimized in view of space and power constraints for purposes of address translation by providing RAM-based storage means of pred... | 12/22/1987 |
| 4712176 | Serial channel interface with method and apparatus for handling data streaming and data interlocked modes of data transfer Data is transferred between a channel and a control unit in interlocked mode or in data streaming mode over a conventional parallel bus and a serial link that permits the control unit and the channel to be located farther apart than the length of the para... | 12/08/1987 |
| 4703416 | Apparatus for locating programs resident on a cartridge of a cartridge programmable communication system A communication system controller is operable under program calls from two memories which are independently changeable. A first memory includes a group of hardware-dependent programs and a second memory includes a group of hardware-independent programs. C... | 10/27/1987 |
| 4691281 | Data processing system simultaneously carrying out address translation of a plurality of logical addresses In a data processing system for use in carrying out address translation of a preselected logical address so as to access a sequence of data elements stored in a memory (32) with an interval left between two adjacent ones of the data elements, a request co... | 09/01/1987 |
| 4689764 | Method and apparatus for formatting a line of text containing a complex character prior to text justification A word or text processing system has a bidirectional printer with formatting capability. A line of text is printed in one direction, and the printer is backspaced to form complex characters by adding overstrikes, such as underlining or accent marks. The f... | 08/25/1987 |
| 4689767 | Magnetic tape drive controller utilizing dual DMA controllers A controller for use with a magnetic tape drive which has a plurality of buffer memories for temporarily storing data that is passed between the tape drive and a host computer system. Temporary storage of data within the tape controller allows data to be ... | 08/25/1987 |
