U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

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Examiner: Huisman, David J.


Primary examiner statistics: 19 patents; average approval time: 86 days
Assistant examiner statistics: 68 patents; average approval time: 1715 days

Patents as Primary Examiner

Patent No. Patent Title:
7562206 Multilevel scheme for dynamically and statically predicting instr...
7464255 Using a shuffle unit to implement shift operations in a processor
7461235 Energy-efficient parallel data path architecture for selectively ...
7447877 Method and apparatus for converting memory instructions to prefet...
7447879 Scheduling instructions in a cascaded delayed execution pipeline ...
7447884 Multi-table branch prediction circuit for predicting a branch's t...
7441102 Integrated circuit with functional state configurable memory and ...
7434032 Tracking register usage during multithreaded processing using a s...
7430653 Pipelined processor with multi-cycle grouping for instruction dis...
7426628 Run-time node prefetch prediction in dataflow graphs
7404069 Branch tracing generator device and method for a microprocessor s...
7363467 Dependence-chain processing using trace descriptors having depend...
7363472 Memory access consolidation for SIMD processing elements having a...
7363476 Method and apparatus to support an expanded register set
7360059 Variable width alignment engine for aligning instructions based o...
7360028 Explicit store-to-instruction-space instruction for self-modifyin...
7360063 Method for SIMD-oriented management of register maps for map-base...
7356673 System and method including distributed instruction buffers for s...
7356674 Method and apparatus for fetching instructions from the memory su...

Patents as Assistant Examiner (view all)

Patent No. Patent Title:
7310723 Methods and systems employing a flag for deferring exception hand...
7290124 Data processor employing register banks with overflow protection ...
7284115 Processor which overrides default operand size for implicit stack...
7281119 Selective vertical and horizontal dependency resolution via split...
7278012 Method and apparatus for efficiently accessing first and second b...
7272701 Method and apparatus for limiting ports in a register alias table...
7272703 Program controlled embedded-DRAM-DSP architecture and methods
7260711 Single instruction multiple data processing allowing the combinat...
7240185 Computer system with two debug watch modes for controlling execut...
7237088 Methods and apparatus for providing context switching between sof...
7237093 Instruction fetching system in a multithreaded processor utilizin...
7228402 Predicate register file write by an instruction with a pending in...
7213135 Method using a dispatch flush in a simultaneous multithread proce...
7203827 Link and fall-through address formation using a program counter p...
7203825 Sharing information to reduce redundancy in hybrid branch predict...
7200740 Apparatus and method for speculatively performing a return instru...
7191310 Parallel processor and image processing apparatus adapted for non...
7191315 Method and system for tracking and recycling physical register as...
7181595 Method for decoding composite VLIW packets utilizing a tree struc...
7171546 CPU life-extension apparatus and method
7171543 Method and apparatus for executing a 32-bit application by confin...
7149880 Method and apparatus for instruction pointer storage element conf...
7149883 Method and apparatus selectively to advance a write pointer for a...
7146489 Methods for intelligent caching in an embedded DRAM-DSP architect...
7134004 Processing device for buffering sequential and target sequences a...
7124281 Processing system having sequential address indicator signals
7114058 Method and apparatus for forming and dispatching instruction grou...
7111152 Computer system that operates in VLIW and superscalar modes and h...
7093109 Network processor which makes thread execution control decisions ...
7093105 Method and apparatus for determining availability of a queue to w...
7082516 Aligning instructions using a variable width alignment engine hav...
7076636 Data storage system having an improved memory circuit board confi...
7069426 Branch predictor with saturating counter and local branch history...
7047398 Analyzing instruction completion delays in a processor
7039790 Very long instruction word microprocessor with execution packet s...
7039795 System and method for using a two-stage multiplexing architecture...
7032104 Configurable hardware register stack for CPU architectures
6988185 Select-free dynamic instruction scheduling
6988190 Method of an address trace cache storing loop control information...
6973563 Microprocessor including return prediction unit configured to det...
 
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