Did You Know...
...that after Parker Brothers executives turned down the game of Monopoly because it had "52 fundamental errors" (including taking too long to play), a copy of the game wound up in the home of the company president who stayed up until 1 a.m. to finish playing it? He was so impressed by the game that the next day he wrote to inventor Charles Darrow and offered to buy it!
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| Number | Title | Issue Date |
| 4739193 | Drive circuit with limited signal transition rate for RFI reduction An amplifier applies turn-on bias to the gate electrode of an output field-effect transistor in response to a first level of an input signal applied to the amplifier. A switched power source supplies operating current to the amplifier for developing the t... | 04/19/1988 |
| 4604535 | FET-bipolar switching device and circuit A switching device and circuit comprises a bipolar transistor and at least two field effect transistors for controlling the bipolar transistor. A first field effect transistor has its drain and source connected across the collector-base of the bipolar tra... | 08/05/1986 |
| 4544851 | Synchronizer circuit with dual input A digital synchronizer circuit including an input to receive an asynchronous level and a second input to receive an ansynchronous pulse. Both inputs are connected to the synchronizer input circuitry which will provide a level output for either type of inp... | 10/01/1985 |
| 4520283 | Band pass filter with a switched capacitor A switched capacitor circuit has: first and second power sources; an operational amplifier driven by the power sources; a feedback capacitor connected to the inverting input terminal and the output terminal of the amplifier; a switched capacitor connected... | 05/28/1985 |
| 4518875 | Three-level MOS logic circuit A ternary logic circuit comprises a load element connected to one voltage level and to a node and a logic section connected to a second voltage level and the same node from which the circuit output is derived. The two voltage levels including the voltage ... | 05/21/1985 |
| 4514650 | Low power small area PLA A logic array includes multiple gated current sources for receiving respective logic input signals, each of the gated current sources is coupled to a respective pair of row conductors and sends current to one row conductor or the other of that pair to ind... | 04/30/1985 |
| 4510451 | Prefire identification for pulse power systems Prefires in a high-power, high-frequency, multi-stage pulse generator are detected by a system having an EMI shielded pulse timing transmitter associated with and tailored to each stage of the pulse generator. Each pulse timing transmitter upon detection ... | 04/09/1985 |
| 4507576 | Method and apparatus for synthesizing a drive signal for active IC testing including slew rate adjustment A special purpose pulse amplifier with programmable high and low levels for complex IC testing is disclosed. Its output has independently programmable positive and negative transition rates and is reverse terminated in 50 ohms. It also has the ability to ... | 03/26/1985 |
| 4506175 | Digital phase comparator circuit producing sign and magnitude outputs A phase detector for digital signals, such as television sync signals, provides a signed short path output of the phase difference between the signals. It features a means for determining which of the signals is leading and lagging, which means also provi... | 03/19/1985 |
| 4506165 | Noise rejection Set-Reset Flip-Flop circuitry Set-Reset Master-Slave Flip-Flop circuitry uses a feedback circuit connected to a circuitry output terminal and to set and reset input terminals to limit the effect of spurious signals such that only signals applied to set and reset terminals which are of... | 03/19/1985 |
| 4506173 | Low power partitioned PLA A logic array includes a plurality of gated current sources which receive respective input signals, each of said gated current sources is coupled to a respective row conductor and sends current to that row conductor when the received input signal is in a ... | 03/19/1985 |
| 4503342 | Low power push-pull CMOS driver circuit The control power input of a power stage designed in the form of a CMOS inverter can be considerably reduced according to the invention in that, with the aid of a driver stage splitting the digital input signal, each of the two gate electrodes of the two ... | 03/05/1985 |
| 4503343 | Active pull-up circuit Provided is an active pull-up circuit which comprises a MOS capacitor having one end connected to an input terminal receiving a pull-up signal, a first MOS transistor having a current path connected between the other end of said MOS capacitor and a signal... | 03/05/1985 |
| 4503550 | Dynamic CCD input source pulse generating circuit A pulse generator circuit for applying a pulse signal to the input source electrode of a charge coupled device (CCD) having a "fill and spill" input operation, includes a voltage reference circuit for generating the "fill" voltage level of the pulse signa... | 03/05/1985 |
| 4501979 | Current amplifier having multiple selectable outputs A current amplifier is provided having a single control amplifier and a plurality of output stages. The desired output stage is digitally selected. The ratios of the output stage currents may be selected during the metalization process. A single capacitor... | 02/26/1985 |
| 4502014 | Coincident pulse cancelling circuit A circuit responsive to pulses on first and second input signal lines for blocking the propagation of these pulses and inhibiting the production of corresponding pulses on output lines when pulses are present at the same time on the input lines and for pr... | 02/26/1985 |
| 4501976 | Transistor-transistor logic circuit with hysteresis A TTL circuit having a pair of current sources (R2/VCC and R2/VCC) and a pair of transistors (Q1 and Q2) arranged in a standard TTL input/inverting configuration has hysteresis at the input signal (VX) for providing noise ... | 02/26/1985 |
| 4501977 | AND-OR logic circuit including a feedback path A plurality of logical product signals, from an AND circuit having a plurality of series circuits of transistors of a first conductivity type which selectively receive input signals, are selectively supplied to the gates of transistors of a second conduct... | 02/26/1985 |
| 4500801 | Self-powered nonregenerative fast gate turn-off FET A fast turn-off FET circuit is provided by a bipolar transistor in the gate circuit of the FET. The bipolar transistor is driven into conduction by residual charge in the gate to source capacitance of the FET upon turn-off of the latter due to removal of ... | 02/19/1985 |
| 4500802 | Three terminal bidirectional source to source FET circuit A three terminal bidirectional FET circuit is provided by first and second MOSFETs connected source to source in series relation between first and second main terminals, and by gating circuitry including current source means connected to a gate terminal f... | 02/19/1985 |
| 4499387 | Integrated circuit formed on a semiconductor substrate with a variable capacitor circuit A MOS type semiconductor integrated circuit comprising a C-MOS inverter including P- and N-channel MOS transistors connected in series between VDD and VSS power supply terminals, the gates of the MOS transistors being supplied with a... | 02/12/1985 |
| 4498022 | Tristate output buffer with high-impedance state responsive to increase in power supply voltage An output buffer circuit capable of three-output states of high and low levels and a high impedance. The output buffer circuit includes a detector circuit for detecting that a power source voltage for the buffer circuit is particularly high and for turnin... | 02/05/1985 |
| 4496850 | Semiconductor circuit for enabling a quick rise of the potential _on the word line for driving a clock signal line A semiconductor circuit for driving a clock signal line comprising a first circuit for pulling up the potential of the clock signal line to the source voltage and a second circuit for pulling down the potential of the clock signal line to a lower voltage.... | 01/29/1985 |
| 4496857 | High speed low power MOS buffer circuit for converting TTL logic signal levels to MOS logic signal levels MOS semiconductor address buffer for converting TTL logic states to a MOS logic state requiring only a single clock and having improved power efficiency. The address buffer operates in response to the single clock pulse to set a latch and connect the latc... | 01/29/1985 |
| 4496851 | Dynamic metal oxide semiconductor field effect transistor clocking circuit A dynamic metal oxide field effect transistor clocking circuit provides at least one output at a fixed time interval after receiving an input. This clocking circuit includes a first stage which further includes a node connected to the first stage output a... | 01/29/1985 |
| 4496859 | Notch filter system A notch filter system for eliminating a specific "stop" frequency from an AC electrical input signal, such as 60 Hz "hum" from an audio program signal. An L/C tuned circuit that is tuned to the stop frequency is used to develop a modified input signal tha... | 01/29/1985 |
| 4495426 | Low power inverter circuit A circuit that precharges a node and conditionally discharges the node according to the value of an input. This circuit also includes a device to isolate the node from the output line during precharge. This circuit can be fabricated as a positive channel ... | 01/22/1985 |
| 4495427 | Programmable logic gates and networks The network connections of the channels of complementary symmetry MOS FET's in a logic gate or array are altered electrically to program different logic responses to logic inputs. To this end, certain of the FET's are gate-injection or substrate-injection... | 01/22/1985 |
| 4494016 | High performance MESFET transistor for VLSI implementation A gallium arsenide buffer amplifier for use in a very large scale integrated circuits is provided. The transistor device in the buffer amplifier has a uniform depth N+ source, gate and drain region and the N+ dopant concentration is made very high which e... | 01/15/1985 |
| 4494073 | Frequency generator using composite digitally controlled oscillators A frequency generator for generating a large number of closely and evenly spaced frequencies over a large bandwidth including a first digitally controlled oscillator and a second digitally controlled oscillator, and a combiner for mixing the frequencies f... | 01/15/1985 |
| 4494018 | Bootstrapped level shift interface circuit with fast rise and fall times An input circuit for a field effect transistor (FET) storage is described which consists of a bootstrap inverter which by a dynamically operating charge-up circuit is supplemented for charging up the bootstrap node to the full operating voltage, and which... | 01/15/1985 |
| 4494021 | Self-calibrated clock and timing signal generator for MOS/VLSI circuitry A self-calibrated clock and timing signal generator provides reliable and continuous arbitrary digital waveforms of preselectable edge resolution. The generator comprises a multistage means to produce a time delayed signal of preselectable edge resolution... | 01/15/1985 |
| 4492883 | Unpowered fast gate turn-off FET A fast turn-off MOSFET circuit is provided by a JFET in the gate circuit of the MOSFET which is connected to the same gate drive terminal as the MOSFET. The JFET becomes conductive upon turn-off of the MOSFET due to removal of gate drive. Conduction of th... | 01/08/1985 |
| 4491747 | Logic circuit using depletion mode field effect switching transistors A logic circuit using depletion-mode field effect switching transistors, wherein, a plurality of logic elements respectively having at least one depletion-mode switching FET are connected in series. The source electrodes of the switching FETs are maintain... | 01/01/1985 |
| 4491745 | TTL flip-flop with clamping diode for eliminating race conditions A master slave flip-flop includes a data gate for receiving the input data and generating therefrom first and second internal data signals, and a master section for latching the internal data signals and for transmitting such signals to a slave section du... | 01/01/1985 |
| 4490633 | TTL to CMOS input buffer A TTL to CMOS input buffer accomplishes buffering a TTL signal to a CMOS signal without static current flow when the TTL is a logic "1" by isolating the input from an input P channel transistor and using feedback from an input N channel transistor to turn... | 12/25/1984 |
| 4490629 | High voltage circuits in low voltage CMOS process A CMOS push-pull output buffer (171) is constructed utilizing a plurality of N channel transistors (74, 75, 76) and a plurality of P channel transistors (71, 72, 73) connected in series. The voltages applied to the gates of the N channel transistors and P... | 12/25/1984 |
| 4490631 | Totem pole/open collector selectable output circuit A Schottky driver is disclosed in which the output circuitry is pin selectable totem pole or open collector configuration. Means for reduced propagation delay are present along with means for reducing totem pole current spikes and overall current drain.... | 12/25/1984 |
| 4489245 | D.C. Voltage bias circuit in an integrated circuit In an integrated circuit having an amplifier with its input terminal connected to a signal input terminal, a D.C. voltage bias circuit is provided which includes a D.C. bias voltage generator and a depletion mode MOS transistor connected at its source-dra... | 12/18/1984 |
| 4489279 | Variable-frequency oscillator having a crystal oscillator A highly stable, tunable oscillator circuit includes a crystal oscillator providing a reference pulse signal of frequency Fco, a voltage-to-frequency converter responsive to a control voltage for providing a control pulse signal of frequency Fv substantia... | 12/18/1984 |
