| Patent No. | Patent Title: |
| 4645546 | Semiconductor substrate |
| 4642880 | Method for manufacturing a recessed semiconductor device |
| 4642144 | Proximity doping of amorphous semiconductors |
| 4638551 | Schottky barrier device and method of manufacture |
| 4637128 | Method of producing semiconductor device |
| 4633573 | Microcircuit package and sealing method |
| 4631806 | Method of producing integrated circuit structures |
| 4630355 | Electric circuits having repairable circuit lines and method of m... |
| 4627151 | Automatic assembly of integrated circuits |
| 4625391 | Semiconductor device and method for manufacturing the same |
| 4624047 | Fabrication process for a dielectric isolated complementary integ... |
| 4622736 | Schottky barrier diodes |
| 4622082 | Conditioned semiconductor substrates |
| 4615865 | Overlay coatings with high yttrium contents |
| 4613885 | High-voltage CMOS process |
| 4611389 | Low-cost power device package with quick-connect terminals and ... |
| 4611386 | Method of producing a semiconductor device |
| 4608749 | Method of manufacturing a solid-state image pickup device |
| 4608095 | Gettering |
| 4608096 | Gettering |
| 4608097 | Method for producing an electronically passivated surface on crys... |
| 4603468 | Method for source/drain self-alignment in stacked CMOS |
| 4602420 | Method of manufacturing a semiconductor device |
| 4601097 | Method of producing thin-film transistor array |
| 4596069 | Three dimensional processing for monolithic IMPATTs |
| 4596071 | Method of making semiconductor devices having dielectric isolatio... |
| 4596070 | Interdigitated IMPATT devices |
| 4593456 | Pyroelectric thermal detector array |
| 4593453 | Two-level transistor structures and method utilizing minimal area... |
| 4592128 | Method for fabricating integrated circuits with polysilicon resis... |
| 4590664 | Method of fabricating low noise reference diodes and transistors |
| 4588455 | Planar diffusion source |
| 4584762 | Lateral transistor separated from substrate by intersecting slots... |
| 4584763 | One mask technique for substrate contacting in integrated circuit... |
| 4583283 | Electrically isolated semiconductor power device |
| 4580331 | PNP-type lateral transistor with minimal substrate operation ... |
| 4577398 | Method for mounting a semiconductor chip |
| 4575919 | Method of making heteroepitaxial ridge overgrown laser |
| 4574467 | N- well CMOS process on a P substrate with double field guard rin... |
| 4574469 | Process for self-aligned buried layer, channel-stop, and isolatio... |
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