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| Number | Title | Issue Date |
| 8090930 | Method and circuits for early detection of a full queue In a pipelined computer architecture in which instructions may be removed from the instruction queue out of sequence, instruction queue status at a cycle K is determined by adding together the number of invalid instructions or free rows in the queue during cycle K... | 01/03/2012 |
| 7464251 | Method and apparatus for configuring arbitrary sized data paths comprising multiple context processing elements A method and an apparatus for configuring arbitrary sized data paths comprising multiple context processing elements (MCPEs) are provided. Multiple MCPEs may be chained to form wider-word data paths of arbitrary widths, wherein a first ALU serves as the most signifi... | 12/09/2008 |
| 7461237 | Method and apparatus for suppressing duplicative prefetches for branch target cache lines A system that suppresses duplicative prefetches for branch target cache lines. During operation, the system fetches a first cache line into in a fetch buffer. The system then prefetches a second cache line, which immediately follows the first cache line, into the fe... | 12/02/2008 |
| 7454601 | N-wide add-compare-select instruction The present invention relates to a method and system for providing an N-wide add-compare-select instruction includes decoding an instruction as an N-wide add-compare-select instruction and selecting a plurality of branch metrics. The method also includes combining t... | 11/18/2008 |
| 7447880 | Processor with internal memory configuration A processor comprises an arithmetic unit for processing operands, a register memory for storing operands with a register memory space and a register memory configuration unit. The register memory configuration unit is designed to configure the register memory such t... | 11/04/2008 |
| 7447886 | System for expanded instruction encoding and method thereof A system and methods are discussed for providing additional capabilities to some instructions associated with loop execution. A standard set of instructions is processed using only a standard instruction size. Some loop instructions are processed with a standard ins... | 11/04/2008 |
| 7447876 | System and method for handling load and/or store operations in a superscalar microprocessor The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose i... | 11/04/2008 |
| 7444495 | Processor and programmable logic computing arrangement A computing arrangement including a processor and programmable logic. In various embodiments, the arrangement includes an instruction processing circuit coupled to a programmable logic circuit, and a memory arrangement coupled to the instruction processing circuit a... | 10/28/2008 |
| 7441103 | High-performance, superscalar-based computer system with out-of-order instruction execution A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program orde... | 10/21/2008 |
| 7441104 | Parallel subword instructions with distributed results The present invention provides for parallel subword instructions that cause results to be non-contiguously stored in a result register. For example, a targeting-type instruction can specify (implicitly or explicitly) a bit position and the result of each of the para... | 10/21/2008 |
| 7426631 | Methods and systems for storing branch information in an address table of a processor Methods and systems for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address t... | 09/16/2008 |
| 7424594 | Efficient complex multiplication and fast fourier transform (FFT) implementation on the ManArray architecture Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with specialized complex multiplication instructions and communication operations... | 09/09/2008 |
| 7424597 | Variable reordering (Mux) instructions for parallel table lookups from registers Parallel table lookups are implemented using variable Mux instructions to reorder data. Table data can be represented in a “table” register, while the desired ordering can be represented in an “Index” register. A direct variable Mux instruction can specify t... | 09/09/2008 |
| 7424598 | Data processor The data processor for executing, instructions realized by wired logic, by a pipeline system, includes a plurality of instruction registers, and arithmetic operation units of the same number. A plurality of instructions read in the instruction registers in one machi... | 09/09/2008 |
| 7424595 | System for managing circuitry of variable function information processing circuit and method for managing circuitry of variable function information processing circuit Configuration management information having circuit configuration information for altering a circuit configuration of an FPGA (12) is stored in a memory (13), the configuration management information according to information related to an instruction g... | 09/09/2008 |
| 7415602 | Apparatus and method for processing a sequence of jump instructions An apparatus for processing a sequence of instructions, which comprises a LCALL instruction, a FCALL instruction and a common re-jump instruction (return), comprises a means for reading-in an instruction, to perform the read-in instruction of a means for examining t... | 08/19/2008 |
| 7412590 | Information processing apparatus and context switching method An information processing apparatus which, when executing a plurality of predetermined units of processing, executes the predetermined units of processing in parallel by a processor by switching between contexts associated with the respective predetermined units. Th... | 08/12/2008 |
| 7404067 | Method and apparatus for efficient utilization for prescient instruction prefetch Embodiments of an apparatus, system and method enhance the efficiency of processor resource utilization during instruction prefetching via one or more speculative threads. Renamer logic and a map table are utilized to perform filtering of instructions in a speculati... | 07/22/2008 |
| 7401211 | Method for converting pipeline stalls caused by instructions with long latency memory accesses to pipeline flushes in a multithreaded processor In a multi-threaded processor, a long latency data dependent thread is flushed from the execution pipelines. Once the stalled thread is flushed, the non-stalling threads in the pipeline can continue their execution. Several resources are used to reduce this unwanted... | 07/15/2008 |
| 7395412 | Apparatus and method for extending data modes in a microprocessor An apparatus and method are provided for extending a microprocessor instruction set beyond its current capabilities to allow for extended size operands specifiable by programmable instructions in the microprocessor instruction set. The apparatus includes translation... | 07/01/2008 |
| 7386710 | Methods and apparatus for scalable array processor interrupt detection and response Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable ... | 06/10/2008 |
| 7386707 | Processor and program execution method capable of efficient program execution A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select ... | 06/10/2008 |
| 7380110 | Branch prediction structure with branch direction entries that share branch prediction qualifier entries An efficient branch prediction structure is described that bifurcates a branch prediction structure into at least two portions where information stored in the second portion is aliased amongst multiple entries of the first portion. In this way, overall storage (and ... | 05/27/2008 |
| 7376820 | Information processing unit, and exception processing method for specific application-purpose operation instruction In the control section, an operation instruction not prescribing a functional specification, and a unit for processing the specific application-purpose operation instruction is provided within the processor core. The structure of this unit can be changed based on a ... | 05/20/2008 |
| 7376818 | Program translator and processor Multiple instructions, specifying equivalent operations but designating different execution units, are stored beforehand on an instruction exchange table. First, a primary compiler compiles a source program into a set of machine-readable instructions. From the set o... | 05/20/2008 |
| 7366874 | Apparatus and method for dispatching very long instruction word having variable length Apparatus and method for dispatching a very long instruction word (VLIW) instruction having a variable length are provided. The apparatus for dispatching a VLIW instruction includes a packet buffer for storing at least one or more VLIW instructions, and a decoding u... | 04/29/2008 |
| 7360066 | Boolean processor A processor including a Boolean logic unit, wherein the Boolean logic unit is operable for performing the short-circuit evaluation of Conjunctive Normal Form Boolean expressions/operations, a plurality of input/output interfaces, wherein the plurality of input/outpu... | 04/15/2008 |
| 7346760 | Data processing apparatus of high speed process using memory of low speed and low power consumption When fetching an instruction from a plurality of memory banks, a first pipeline cycle corresponding to selection of a memory bank and a second pipeline cycle corresponding to instruction readout are generated to carry out a pipeline process. Only the selected memory... | 03/18/2008 |
| 7340585 | Method and system for fast linked processor in a system on a chip (SoC) A fast linked multiprocessor network (22) including a plurality of processing modules (24, 26, 28, 30, 32, and 34) implemented on a field programmable gate array (10) and a plurality of configurable uni-directional links (21, 23, 25, 2... | 03/04/2008 |
| 7328328 | Non-temporal memory reference control mechanism An apparatus and method are provided for extending a microprocessor instruction set to specify non-temporal memory references at the instruction level. The apparatus includes translation logic and extended execution logic. The translation logic translates an extende... | 02/05/2008 |
| 7315932 | Data processing system having instruction specifiers for SIMD register operands and method thereof Various load and store instructions may be used to transfer multiple vector elements between registers in a register file and memory. A cnt parameter may be used to indicate a total number of elements to be transferred to or from memory, and an rcnt parameter may be... | 01/01/2008 |
| 7315936 | Enhanced boolean processor A set of processors, co-processors and processor cores having a Boolean logic unit, wherein the Boolean logic unit is operable, respectively, for performing the short-circuit evaluation of Conjunctive Normal Form Boolean expressions/operations, Disjunctive Normal Fo... | 01/01/2008 |
| 7308560 | Processing unit A digital signal processing unit includes a control unit and a data computing unit. An R/L register for distinguishing independent data is disposed in the control unit. An R/L select signal for indicating independent data is supplied to the data computing unit. A da... | 12/11/2007 |
| 7305540 | Method and apparatus for data processing Methods and apparatuses for a data processing system are described herein. In one aspect of the invention, an exemplary apparatus includes a chip interconnect, a memory controller for controlling the host memory comprising DRAM memory, the memory controller coupled ... | 12/04/2007 |
| 7302551 | Suppression of store checking An apparatus and method are provided for extending a microprocessor instruction set to allow for selective suppression of store checking at the instruction level. The apparatus includes fetch logic, and translation logic. The fetch logic receives an extended instruc... | 11/27/2007 |
| 7290122 | Dataflow graph compression for power reduction in a vector processor A method and apparatus for power reduction in a processor controlled by multiple-instruction control words. A multiple-instruction control word comprises a number of ordered fields, with each ordered field containing an instruction for an element of the processor. T... | 10/30/2007 |
| 7275148 | Data processing system using multiple addressing modes for SIMD operations and method thereof Various load and store instructions may be used to transfer multiple vector elements between registers in a register file and memory. A cnt parameter may be used to indicate a total number of elements to be transferred to or from memory, and an rcnt parameter may be... | 09/25/2007 |
| 7266672 | Method and apparatus for retiming in a network of multiple context processing elements A method and an apparatus for retiming in a network of multiple context processing elements in a network of multiple context processing elements are provided. A programmable delay element is configured to programmably delay signals between a number of multiple conte... | 09/04/2007 |
| 7237089 | SIMD operation method and SIMD operation apparatus that implement SIMD operations without a large increase in the number of instructions An operation method has processing for applying a same type of operation in parallel to N M-bit operands to obtain N M-bit operation results executed on a computer. Here, N is an integer equal to or greater than 2 and M is an integer equal to or greater than 1. The ... | 06/26/2007 |
| 7237092 | Microprocessor circuit for portable data carriers and method for operating the circuit A microprocessor circuit includes a control unit, a memory for free programming with at least one program having functions, a stack for buffer-storing data, a register bank having at least one register, and an auxiliary register that stores a number of bits, each of... | 06/26/2007 |
