Bizarre Patents
Cloaking System Using Optoelectronically Controlled Camouflage
A Cloaking System designed to operate in the visible light spectrum, utilizes optoelectronics and/or photonic components to conceal an object within it.
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| Number | Title | Issue Date |
| 5465372 | Dataflow computer for following data dependent path processes A dataflow machine for generally following data dependent path processes, the machine including an instruction store, an operand store, a plurality of data dependent path process executors, each process executor including an instruction queue and a queue ... | 11/07/1995 |
| 5455955 | Data processing system with device for arranging instructions A data processing system incorporating a main memory for storing instructions and operands and performing data processing in a mode of microprogram control system in response to instructions read out of the main memory. The system translates an instructio... | 10/03/1995 |
| 5452469 | Command performing order change over system based on information contained in executed command in a data processor A slave controller formed on a single semiconductor substrate executes a built in control algorithm in response to a command supplied from a master controller. Upon completion of command execution, the controls respond to predetermined information contain... | 09/19/1995 |
| 5450605 | Boundary markers for indicating the boundary of a variable length instruction to facilitate parallel processing of sequential instructions The specification discloses a method and apparatus for determining the length of variable-length instructions that appear sequentially in an instruction stream without differentiation. The apparatus may be used to facilitate parallel processing of such va... | 09/12/1995 |
| 5450596 | CD-ROM data retrieval system using a hands-free command controller and headwear monitor A video display attached to a lightweight headpiece and using a zero motion mouse for the input of commands. The system accesses data from a CD-ROM reader and can store user generated data to a memory card for later retrieval. It is light enough to be wor... | 09/12/1995 |
| 5446915 | Parallel processing system virtual connection method and apparatus with protection and flow control A parallel processing system virtual connection method and apparatus with protection and flow control is described. In accordance with the present invention, virtual connections between processor nodes are maintained through the use of connection tables. ... | 08/29/1995 |
| 5446913 | Method and system for nonsequential execution of intermixed scalar and vector instructions in a data processing system utilizing a finish instruction array A method and system for enhancing processing efficiency in a data processing system which includes multiple scalar instruction processors and a vector instruction processor. An ordered sequence of intermixed scalar and vector instructions is processed in ... | 08/29/1995 |
| 5446914 | Twisted pair and attachment unit interface (AUI) coding and transceiving circuit with full duplex, testing, and isolation modes An Ethernet circuit which provides encoder, decoder, twisted pair transceiver, and AUI interface functions in accordance with the IEEE 802.3 standard. In addition, the Ethernet circuit provides a full duplex function for independent transmit and receive p... | 08/29/1995 |
| 5442796 | Pulse generator and demodulator with controlling processor and decrementing counters A central processing unit (CPU) and a dedicated pulse generating and demodulating logic circuit are used to both generate and demodulate a wide variety of pulse signals. Although the CPU exercises general supervision of the dedicated logic circuit, the ci... | 08/15/1995 |
| 5440755 | Computer system with a processor-direct universal bus connector and interchangeable bus translator A universal processor-direct bus structure on a specifically partitioned motherboard uses a separate local bus translator card to adapt to a specific local bus protocol and configuration. The processor-direct bus on the motherboard contains a superset of ... | 08/08/1995 |
| 5440756 | Apparatus and method for real-time extraction and display of musical chord sequences from an audio signal An apparatus and method are provided for processing an audio signal conveying a musical passage so as to reveal the sequence of musical chords contained within that passage. The signal is amplified, filtered, and converted to digital data, which are then ... | 08/08/1995 |
| 5438679 | Data storage apparatus having volatile memory and nonvolatile memory and data indication means for indicating memory storing data Data input from a key switch is displayed on a liquid crystal display, and whether to store the data in a RAM or an EEPROM is selected by a selection switch. If the EEPROM is selected, a CPU turns on a power switch to apply a high voltage to the EEPROM to... | 08/01/1995 |
| 5437043 | Information processing apparatus having a register file used interchangeably both as scalar registers of register windows and as vector registers An arrangement having a register file having registers greater in number than those which are designated by an instruction, a pipeline ALU, a current window pointer and window number modifier operating in a register window mode, an element counter and add... | 07/25/1995 |
| 5428805 | Method and apparatus for recognizing and performing handwritten calculations A pen-based calculator recognizes handwritten input. The calculator comprises a display simulating a sheet of paper, and a stylus simulating a pen. The user writes a calculation on the calculator as if it were a piece of scratch paper. The calculator uses... | 06/27/1995 |
| 5426783 | System for processing eight bytes or less by the move, pack and unpack instruction of the ESA/390 instruction set A processing system comprising a first means for generating first signals indicating when the next instruction can begin processing where eight or less bytes are processed by the MOVE, PACK or UNPACK instruction, a second means for generating second signa... | 06/20/1995 |
| 5422837 | Apparatus for detecting differences between double precision results produced by dual processing units operating in parallel In order to validate data manipulation results in a CPU which incorporates duplicate BPUs for integrity, which BPUs are typically each implemented on a single VLSI circuit chip, and which is capable of performing single and double precision data manipulat... | 06/06/1995 |
| 5423051 | Execution unit with an integrated vector operation capability A vector operation capability is integrated into the execution unit (E-Unit) portion of a computing systems central processing unit (CPU) designed to support scalar instruction processing. The fixed point and floating point instruction functional units in... | 06/06/1995 |
| 5421022 | Apparatus and method for speculatively executing instructions in a computer system A compiler groups instructions into sets. The sets of instructions are related by data and control dependencies which are unresolvable by the compiler. Sets of instructions having unresolved dependencies are executed in a speculative state of the computer... | 05/30/1995 |
| 5421020 | Counter register implementation for speculative execution of branch on count instructions A data processing system for speculatively executing instructions. The data processing system includes a memory for storing instructions at addresses which can be generated by a branch unit in a processor. The processor also has a count register for stori... | 05/30/1995 |
| 5418974 | Circuit design method and system therefor A system and method for designing a structure such as a circuit. First the sensitivity of a circuit performance function (sensitivity data set - SDS) to at least one physical parameter is determined. Then, an estimated distribution of the design function ... | 05/23/1995 |
| 5418976 | Processing system having a storage set with data designating operation state from operation states in instruction memory set with application specific block The core DSP is extended to a functional module extension, for example having extended memory and input/output circuitry, which extended module is mapped in the address base of the data storage of the core DSP, whereby an ASIC-expanded LSI may be wholly f... | 05/23/1995 |
| 5410722 | Queue system for dynamically allocating and moving memory registers between a plurality of pseudo queues A plurality of queues where each queue is defined by a set of criteria, the queue system comprises a plurality of header registers where each header register defines a queue in the queue system and a plurality of task registers where each task register ca... | 04/25/1995 |
| 5408672 | Microcomputer having ROM to store a program and RAM to store changes to the program When an error is found in a program of the microcomputer, there are stored in a writable memory change address data of an address of a wrong instruction to be subjected to modification or insertion in the read-only memory, change instruction codes of modi... | 04/18/1995 |
| 5406644 | Apparatus and method for emulating a computer instruction set using a jump table in the host computer Data processing means adapted to be controlled by sequential instructions, a substantial number of which comprise an operation code selected from a set of n such codes and a qualifying code selected from a set of m such codes, the data processing means co... | 04/11/1995 |
| 5404557 | Data processor with plural instruction execution parts for synchronized parallel processing and exception handling A data processor with plural instruction execution parts for synchronized parallel processing which generates first information indicating the order of each group of instructions having successive instruction addresses and second information indicating th... | 04/04/1995 |
| 5404556 | Apparatus for carrying out asynchronous communication among integrated circuits An apparatus for carrying out asynchronous communication among integrated circuits for inter-chip communications includes a plurality of senders disposed on an integrated circuit. Each is associated with send-initiate circuitry to indicate a request to se... | 04/04/1995 |
| 5404551 | Parallel processor which processes instructions, after a branch instruction, in parallel prior to executing the branch instruction and its parallel processing method In a typical operating system, one-third of a program consists of branch instructions. This means a performance of a processor of a typical operating system depends greatly on whether or not an instruction before and after a branch instruction can be exec... | 04/04/1995 |
| 5396634 | Method and apparatus for increasing the decoding speed of a microprocessor Apparatus for increasing the decoding speed of a microprocessor. The apparatus includes a first decoder for decoding macroinstructions. The first decoder includes apparatus for generating a single initial microinstruction vector from simple macroinstructi... | 03/07/1995 |
| 5394553 | High performance array processor with nonlinear skewing of elements An array processor is described with N processing elements, N memory modules, and an interconnection network that allows parallel access and alignment of rows, columns, diagonals, contiguous blocks, and distributed blocks of N×N arrays. The memory system... | 02/28/1995 |
| 5394557 | State machine operating in multiple parallel phase and method thereof A state machine circuit comprising a first phased circuit clocked by a first phased clock and a second phased circuit clocked by a second phased clock. The first phased circuit includes a first input register which sequences and stores at least one input ... | 02/28/1995 |
| 5392444 | Programmable controller for completing the execution of a block of user programs within a set time period A programable controller includes a cycle time setter, a counter, and a calculator. The cycle time setter sets a cycle time for one round of execution of a sequential series of processing routines. The counter counts an execution time between the start of... | 02/21/1995 |
| 5386519 | Information processing apparatus incorporating buffer storing a plurality of branch target instructions for branch instructions and interrupt requests An information processing apparatus is provided with a buffer and accompanying circuitry for retrieving instruction code at a branch target address and providing that code to an execution unit within a single clock, much more quickly than the one bus cycl... | 01/31/1995 |
| 5379442 | Fast primary and feedback path in a programmable logic circuit A plurality of programmable circuits joining input terminals to output terminals in a product term of a programmable logic circuit. Each circuit includes a first multiplexor joining an input terminal to a first node, a second multiplexor joining an output... | 01/03/1995 |
| 5377358 | Character processing device adapted to perform document-editing processing and typewriting processing A character processing device adapted to perform document-editing processing and typewriter processing of information. The device includes a switch for switching the device between document-editing processing and typewriter processing. Also provided are f... | 12/27/1994 |
| 5367691 | Pipe-staggered apparatus and method utilizing carry look-ahead signal processing An apparatus (100, 200) and method (300, 400) include an improved architecture for data processing that maintains data throughput while maintaining a reasonable circuit complexity. The method utilizes a system of calculating subsets of desired results tha... | 11/22/1994 |
| 5367692 | Parallel computer system including efficient arrangement for performing communications among processing node to effect an array transposition operation A processing element array and a controller. The processing element array comprises a plurality of processing element nodes interconnected by a plurality of communications links in the form of a hypercube. Each processing element node has a memory includi... | 11/22/1994 |
| 5363507 | Method and system for storing and retrieving collaboratively processed information by associated identification data A collaborative information processing system is formed of a plurality of terminal units interconnected through a network. Each terminal unit includes a microprocessor provided with a control program for controlling the execution of various application pr... | 11/08/1994 |
| 5361392 | Digital computing system with low power mode and special bus cycle therefor A digital computing system having a low power mode of operation includes a mechanism for communicating, prior to entering the low power mode, information determinative of which events shall be capable of causing the termination of the low power mode. An i... | 11/01/1994 |
| 5361371 | Microprocessor with reset execution from an arbitrary address A microprocessor which, following a reset signal, permits execution beginning from an arbitrary address. The microprocessor is constituted in a manner such that arbitrary data is set in advance in a data register as an address. The address in the data reg... | 11/01/1994 |
| 5355506 | Communication method for controlling and monitoring robotic entities The method for routing communications is designed for a particular set of tities including at least one robotic vehicle and a control center governing the vehicle. The method includes the construction of variable length informational transmissions whose c... | 10/11/1994 |
