| Patent No. | Patent Title: |
| 8065457 | Delayed memory access request arbitration |
| 8041867 | Method and apparatus for enhancing data rate of advanced micro-co... |
| 8024504 | Processor interrupt determination |
| 7457904 | Methods and systems for a reference clock |
| 7457901 | Microprocessor apparatus and method for enabling variable width d... |
| 7444454 | Systems and methods for interconnection of multiple FPGA devices |
| 7441059 | Method and device for data communication |
| 7430629 | Internet SCSI communication via UNDI services |
| 7426599 | Systems and methods for writing data with a FIFO interface |
| 7415556 | Exclusion control |
| 7412555 | Ordering rule and fairness implementation |
| 7406552 | Systems and methods for early fixed latency subtractive decoding ... |
| 7380033 | Communication apparatus implementing time domain isolation with r... |
| 7376777 | Performing an N-bit write access to an M×N-bit-only peripheral |
| 7360007 | System including a segmentable, shared bus |
| 7350004 | Resource management device |
| 7343441 | Method and apparatus of remote computer management |
| 7337253 | Method and system of routing network-based data using frame addre... |
| 7330926 | Interruption control system |
| 7310697 | System and method for dynamic USB power source |
| 7305588 | Testing the interrupt sources of a microprocessor |
| 7305509 | Method and apparatus for zero stub serial termination capacitor o... |
| 7302507 | Reestablishing connections when a block/device at one end is re-i... |
| 7263571 | Bus segment decoder |
| 7263563 | Multi-bus driver apparatus and method for driving a plurality of ... |
| 7260663 | System and method for presenting interrupts |
| 7240137 | System and method for message delivery across a plurality of proc... |
| 7231479 | Round robin selection logic improves area efficiency and circuit ... |
| 7222204 | Testing the interrupt priority levels in a microprocessor |
| 7200701 | System and method for processing system management interrupts in ... |
| 7162564 | Configurable multi-port multi-protocol network interface to suppo... |
| 7143224 | Smart card for performing advance operations to enhance performan... |
| 7139853 | Data transmission/reception system, connection establishing metho... |
| 7133946 | Mechanism to repeat signals across an unrelated link |
| 7127542 | Hot-plugging nodes in a modular system having redundant power sup... |
| 7124230 | Use of bus transaction identification codes |
| 7124228 | Bus communication architecture, in particular for multicomputing ... |
| 7120713 | Systems and methods for interfacing legacy equipment to high-spee... |
| 7117289 | Claiming cycles on a processor bus in a system having a PCI to PC... |
| 7103697 | Flow-through register |
Bizarre Patents 
PatentStorm News
