| Patent No. | Patent Title: |
| 6996677 | Method and apparatus for protecting memory stacks |
| 6996669 | Cluster-based cache memory allocation |
| 6968420 | Use of EEPROM for storage of security objects in secure systems |
| 6965980 | Multi-sequence burst accessing for SDRAM |
| 6944743 | Memory hub bypass circuit and method |
| 6938140 | System and method for linear object reallocation in place |
| 6934807 | Determining an amount of data read from a storage medium |
| 6928531 | Linear and non-linear object management |
| 6920540 | Timing calibration apparatus and method for a memory device signa... |
| 6915400 | Memory access collision avoidance scheme |
| 6910107 | Method and apparatus for invalidation of data in computer systems |
| 6910099 | Disk drive adjusting read-ahead to optimize cache memory allocati... |
| 6910104 | Icache-based value prediction mechanism |
| 6907506 | Security device for a mass storage |
| 6904507 | Buffer management architecture and method for an infiniband subne... |
| 6904492 | Write-once memory device including non-volatile memory for tempor... |
| 6898687 | System and method for synchronizing access to shared resources |
| 6895474 | Synchronous DRAM with selectable internal prefetch size |
| 6895486 | Linear object management for a range of flash memory |
| 6892281 | Apparatus, method, and system for reducing latency of memory devi... |
| 6889299 | Semiconductor integrated circuit |
| 6883074 | System and method for efficient write operations for repeated sna... |
| 6883071 | Method for evaluation of scalable symmetric multiple processor ca... |
| 6880062 | Data mover mechanism to achieve SAN RAID at wire speed |
| 6880043 | Range-based cache control system and method |
| 6880055 | Semiconductor memory device |
| 6877063 | Multiple memory aliasing for a configurable system-on-chip |
| 6877065 | Advanced read cache management |
| 6871262 | Method and apparatus for matching a string with multiple lookups ... |
| 6862660 | Tag memory disk cache architecture |
| 6851022 | Raid controller and control method thereof |
| 6851032 | Latency reduction using negative clock edge and read flags |
| 6851039 | Method and apparatus for generating an interleaved address |
| 6848020 | Command aging method for data storage devices |
| 6845433 | Memory device having posted write per command |
| 6836833 | Apparatus and method for discovering a scratch pad memory configu... |
| 6829689 | Method and system for memory access arbitration for minimizing re... |
| 6826660 | Hierarchical SMP computer system |
| 6807605 | Managing a data storage array, a data storage system, and a raid ... |
| 6801992 | System and method for policy based storage provisioning and manag... |
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