| Patent No. | Patent Title: |
| 5850150 | Final stage clock buffer in a clock distribution network |
| 5793225 | CMOS SONET/ATM receiver suitable for use with pseudo ECL and TTL ... |
| 5773994 | Method and apparatus for implementing an internal tri-state bus w... |
| 5773996 | Multiple-valued logic circuit |
| 5764080 | Input/output interface circuitry for programmable logic array int... |
| 5760607 | System comprising field programmable gate array and intelligent m... |
| 5760606 | High voltage withstanding circuit and voltage level shifter |
| 5757206 | Electronic circuit with programmable gradual power consumption co... |
| 5754061 | Bi-CMOS circuits with enhanced power supply noise suppression and... |
| 5754058 | Output buffer controlling circuit of a multibit integrated circui... |
| 5754062 | Current switching logic type circuit with small current consumpti... |
| 5751161 | Update scheme for impedance controlled I/O buffers |
| 5751165 | High speed customizable logic array device |
| 5751169 | Emitter coupled logic (ECL) gate which generates intermediate sig... |
| 5748009 | Programmable logic cell |
| 5744978 | Variable load device responsive to a circuit parameter |
| 5742178 | Programmable voltage stabilizing circuit for a programmable integ... |
| 5736866 | Active pull-down circuit for ECL using a capacitive coupled circu... |
| 5736870 | Method and apparatus for bi-directional bus driver |
| 5731712 | Programmable gate array for relay ladder logic |
| 5731715 | Glitch-free clock enable circuit |
| 5731713 | TTL to CMOS level translator with voltage and threshold compensat... |
| 5731717 | Logic or memory element based on n-stable phase-locking of s... |
| 5729155 | High voltage CMOS circuit which protects the gate oxides from exc... |
| 5726591 | MESFET logic device with clamped output drive capacity and low po... |
| 5726586 | Programmable application specific integrated circuit and logic ce... |
| 5726582 | Control circuit for keeping constant the impedance of a terminati... |
| 5726587 | BiCMOS tri-state buffer with low leakage current |
| 5719505 | Reduced power PLA |
| 5719507 | Logic gate having transmission gate for electrically configurable... |
| 5717342 | Output buffer incorporating shared intermediate nodes |
| 5714890 | Programmable logic device with fixed and programmable memory |
| 5712581 | Full differential data qualification circuit for sensing a logic ... |
| 5705937 | Apparatus for programmable dynamic termination |
| 5705942 | Method and apparatus for locating and improving critical speed pa... |
| 5703497 | Current source responsive to supply voltage variations |
| 5703501 | Apparatus and method for precharging a bus to an intermediate lev... |
| 5701091 | Routing resources for hierarchical FPGA |
| 5698996 | Data processing with self-timed feature and low power transition ... |
| 5698995 | Clock signal generator and integrated circuit including the clock... |
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