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Vehicular Impact Signaling Device
An apparatus for the deployment of a visible plume to alert other motorists that a proximate motor vehicle has been involved in a collision.
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| Number | Title | Issue Date |
| 6152613 | Circuit implementations for asynchronous processors An asynchronous and delay-insensitive data processor comprises a plurality of components communicating with each other and synchronizing their activities by communication actions on channels and buses. Each component consists of a control part and a data ... | 11/28/2000 |
| 6021472 | Information processing device and control method thereof An operation for achieving consistency among copies existing in a plurality of cache memories in a parallel computer system was performed per transaction. If an access issued from a processor to a cache memory is a synchronous access, seeking of a DIRTY b... | 02/01/2000 |
| 6011913 | Method and apparatus for determination of spacecraft drag A method and apparatus for modeling the exposure of spacecraft-mounted solar power panels to the sun over a given time interval, such as an orbit period, and a method and apparatus for modeling the drag of spacecraft over a given time interval, such as an... | 01/04/2000 |
| 5999720 | Post exposure bake simulation method Disclosed is a post exposure bake simulation method in lithography process to be used for a semiconductor fabrication unit, which has the steps of: expanding an inhibitor concentration distribution to be obtained by exposure calculation according to the b... | 12/07/1999 |
| 5999728 | Method and apparatus for enhancing the portability of an object oriented interface among multiple platforms The present invention is directed to providing an ability to re-host, or port, an object oriented graphical user interface implementation from a native window-based platform, or environment, to another window-based platform, or environment. Exemplary embo... | 12/07/1999 |
| 5995746 | Byte-compare operation for high-performance processor A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations ... | 11/30/1999 |
| 5978576 | Computer performance modeling system and method A computer performance modeling system is provided. The modeling system includes a first and a second submodel which simulate system operations of a particular system component in minute and simple detail, respectively. A performance analysis mechanism is... | 11/02/1999 |
| 5974532 | System and method for generating responses for inputs using a hybrid state engine table A system, method and computer program product for quickly generating responses to vast numbers and types of inputs employs a command response table that includes instructions for generating simple responses and various levels of detailed logical responses... | 10/26/1999 |
| 5970235 | Pre-decoded instruction cache and method therefor particularly suitable for variable byte-length instructions An instruction cache for a superscalar processor having a variable byte-length instruction format, such as the X86 format, is organized as a 16K byte 4-way set-associative cache. An instruction store array is organized as 1024 blocks of 16 predecoded inst... | 10/19/1999 |
| 5966527 | Apparatus, article of manufacture, method and system for simulating a mass-produced semiconductor device behavior A design apparatus, article of manufacture, method and system are disclosed for simulating mass-produced semiconductor device behavior. Drain-to-source current values are obtained from actual semiconductor devices in response to voltage levels at the drai... | 10/12/1999 |
| 5963736 | Software reconfigurable target I/O in a circuit emulation system A time-sliced hardware-based emulator including at least one of: programmable I/O assignment; programmable levels of DC voltage; programmable pull-up or pull-down resistors in the emulator on a pin-by pin basis; programmable forcing and/or disabling of va... | 10/05/1999 |
| 5960181 | Computer performance modeling system and method A computer performance modeling system is provided. The modeling system includes a first and a second submodel which simulate system operations of a particular system component in minute and simple detail, respectively. A performance analysis mechanism is... | 09/28/1999 |
| 5953515 | Pluggable electronic card presence detect scheme for use in parallel and serial vital detect product data (VPD) collection systems A vital product data (VPD) detection circuit mountable on a substrate of a pluggable component. The circuit comprises a "parallel read" circuit for generating vital product data associated with the pluggable component, a "serial read" circuit for storing ... | 09/14/1999 |
| 5953520 | Address translation buffer for data processing system emulation mode A processor and method of operating a processor which has a native instruction set and emulates instructions in a guest instruction set are described. According to the method, a series of guest instructions from the guest instruction set are stored in mem... | 09/14/1999 |
| 5953516 | Method and apparatus for emulating a peripheral device to allow device driver development before availability of the peripheral device A method of emulating a peripheral device in a multiprocessor computer system to test device driver programs. The emulation program is loaded by a host microprocessor into one or more of the other microprocessors (target microprocessors) which are not bei... | 09/14/1999 |
| 5949991 | Fast modeling of signal propagation delays through interconnect wires with arbitrary load distribution A method of analyzing a plurality of signal propagation delays along a plurality of signal interconnection lines within a programmable integrated circuit using a distributed electrical circuit model for the signal interconnection lines which programmably ... | 09/07/1999 |
| 5946472 | Apparatus and method for performing behavioral modeling in hardware emulation and simulation environments In accordance with the present invention, a system for providing high-speed sequential modeling in a simulator or emulator environment is provided. The system includes a sequential control system (microprocessor board) which is attached directly to an emu... | 08/31/1999 |
| 5946471 | Method and apparatus for emulating laboratory instruments at remote stations configured by a network controller An improved laboratory instrument emulation network system is provided having instrument emulation stations and an instrument emulation network controller in which the emulation network system allows communication between the network controller and each i... | 08/31/1999 |
| 5938778 | System and method for tracing instructions in an information handling system without changing the system source code The present invention is directed to a system and method for tracing operations in an information handling system without changing the operating system code. Certain machine registers are shadowed during critical machine state transitions (e.g., taking an... | 08/17/1999 |
| 5933621 | Method and Apparatus for terminal emulation in a semiconductor fabricating facility A method and apparatus for emulating a dedicated terminal in semiconductor fabricator having a back end that includes a source of semiconductor substrates, a transport mechanism for transporting the substrates and a process chamber. A wall separates the b... | 08/03/1999 |
| 5930498 | Apparatus for stably producing discreted grid points A discreted grid producing apparatus is for discreting an analytic region into a plurality of micro-regions of discreted grid points on numerically solving a partial differential equation. The apparatus produces a discreted grid for use in obtaining simul... | 07/27/1999 |
| 5922052 | Fast Ethernet combination chaining of auto-negotiations for multiple physical layer capability A circuit and method for Ethernet combination chaining of auto-negotiation sessions for multiple physical layer capability. The present invention provides control circuitry for arbitrating between different physical layer circuit types that heretofore wer... | 07/13/1999 |
| 5923578 | Data processing circuit A data processing circuit multiplies, by 2a, input data supplied in a time-division multiplexed manner over a plurality of lines. The data processing circuit includes first, second, and third data selectors each having first, second, and third ... | 07/13/1999 |
| 5920712 | Emulation system having multiple emulator clock cycles per emulated clock cycle An emulator system allowing a single cycle in a system clock in a user circuit to be emulated in multiple cycles of the emulator system clock. The emulator system provides a unique architecture permitting gates in the emulator to be used to emulate functi... | 07/06/1999 |
| 5913052 | System and method for debugging digital signal processor software with an architectural view and general purpose computer employing the same A system and method, operable on a general purpose computer, for debugging software that is to control a digital signal processor ("DSP") and a general purpose computer employing either the system or the method. The present invention is employable with ei... | 06/15/1999 |
| 5909568 | Process and apparatus for transferring data between different file formats Disclosed is a process and apparatus for transferring data between an active file being used by an application and an external file that is stored on a storage medium. The active file will preferably have a different format than the external file. The app... | 06/01/1999 |
| 5905882 | Electronic-equipment control apparatus, electronic-equipment control method and electronic-equipment control system An electronic-equipment system is formed by a home switch connected to a telephone, a VCR, an audio apparatus, a-personal computer, a set-top box (decoder) and a television receiver by home data lines. The home switch transmits data received from the piec... | 05/18/1999 |
| 5903744 | Logic emulator using a disposable wire-wrap interconnect board with an FPGA emulation board A hardware-based emulator is partitioned onto two boards. An emulation board has field-programmable gate array (FPGA) chips mounted on a top surface, and connection posts protruding through to the bottom surface. The I/O pins of the FPGA chips that carry ... | 05/11/1999 |
| 5898857 | Method and system for interfacing an upgrade processor to a data processing system A data processing system is disclosed which includes a first processor having an m-byte data width, an n-byte data bus, where n is less than m, and a second processor electrically coupled to the bus which performs bus transactions utilizing n-byte packets... | 04/27/1999 |
| 5886904 | Latch optimization in hardware logic emulation systems A method for optimizing a logical design for emulation. The present invention optimzes latch-based designs by transforming them into a flip-flop based circuit. The design is analyzed to determine whether any consecutive latches are clocked by the same clo... | 03/23/1999 |
| 5887155 | Vertex based geometry engine system for use in integrated circuit design A system and method for processing geometry is provided which reduces the amount of memory needed for processing the geometry while improving the processing speed. The system and method deliver vertices in sequence to a vertex queue so that data in the ve... | 03/23/1999 |
| 5887157 | Local bus interface A local bus interface for providing high-speed data transfer between the local bus of a personal computer and one or more data storage devices. The local bus interface bypasses the standard expansion bus (ISA, EISA, Micro Channel) on the personal computer... | 03/23/1999 |
| 5887182 | Multiprocessor system with vector pipelines In a multiprocessor system having a plurality of processors and main memory common to the processors, each processor includes at least one vector calculation unit which is specific to a vector calculation and which is independent of the vector calculation... | 03/23/1999 |
| 5880974 | Merchandise simulator system and devices A merchandise simulator device which allows a user to operate a desired piece of merchandise on a user's terminal as if the user was using the piece actually at hand. In the merchandise simulator device, when a workstation executes merchandise simulation ... | 03/09/1999 |
| 5875116 | Logic division apparatus The electronic circuits of a large-scale ASIC or logic device are assigned to a plurality of programmable chips with logic block division that enables the finished circuits to operate at appropriate timings. A logic division processing unit divides the el... | 02/23/1999 |
| 5872956 | Design methodology for device drivers supporting various operating systems network protocols and adapter hardware An alterable device driver development system for supporting various operating systems, network protocols, and adapter hardware interfaces. Each device driver comprises a System, Network and Adapter software component, each component providing services to... | 02/16/1999 |
| 5872954 | Method of monitoring registers during emulation A method for reading various registers of a computer system without changing the emulator software. Address register 22, data memory I/O 30 and control register 26 surrounding D-MEM (data memory) 14 are configured as registers of a master/slave latching c... | 02/16/1999 |
| 5870586 | Configuration emulation of a programmable logic device A configuration emulation circuit generates configuration signals to emulate a Programmable Logic Device (PLD) in a configuration timing relationship and a configuration protocol relationship between a programming circuit and the PLD. The circuit includes... | 02/09/1999 |
| 5867688 | Data acquisition and retrieval system with wireless handheld user interface A data retrieval and acquisition system having a wireless handheld interface for data entry by the user. The system includes a communication server for communicating, such as through IR signals, with the handheld interfaces. The communications server comm... | 02/02/1999 |
| 5864489 | Method and apparatus for determining exposure of spacecraft-mounted solar panels to sun and determination of spacecraft drag A method and apparatus for modeling the exposure of spacecraft-mounted solar power panels to the sun over a given time interval, such as an orbit period, and a method and apparatus for modeling the drag of spacecraft over a given time interval, such as an... | 01/26/1999 |
